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研究生:鄭夢涵
研究生(外文):Meng-Han Cheng
論文名稱:改良型矩陣乘法器之設計
論文名稱(外文):Design of an Improved Matrix Multiplier
指導教授:杜迪榕
指導教授(外文):Dyi-Rong Duh
學位類別:碩士
校院名稱:國立暨南國際大學
系所名稱:資訊工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2006
畢業學年度:94
語文別:英文
論文頁數:34
中文關鍵詞:矩陣乘法合併運算定點運算縮小部分乘積矩陣
外文關鍵詞:matrix multiplicationmerged arithmeticfixed-point arithmeticpartial product matrix reduction
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矩陣乘法是科學與工程計算中常見的運算之一,許多人皆為了能增進其計算效率而努力。近幾十年以來,為了加速這類需要龐大計算量的運算,平行處理不外乎為最佳的選擇。隨著硬體製造技術的進步,選擇高速的處理器或是採用多個處理器來執行這類型的運算也非常普遍。在此篇論文中,合併運算將被包含在平行架構中進行。合併運算打破個別的乘法器與加法器的界線,而將乘法與加法視為一體同時執行。然而,在做個別乘積項的加法時,並沒有任一個方法總是最好的。因此,我們提出一個包含之前的方法和新的混合方式來尋找最有效率的一種。有鑒於使用者對系統的考量並不唯一,我們的模擬程式將輸出三種量測標準供使用者選擇,分別是時間,成本和時間乘以成本。除此之外,大致的硬體連接方式也被呈現於結果中,協助之後的實作設計。對於追求高效能以及低成本的系統設計中,此論文將能提供莫大的幫助。
Since matrix multiplication is one of the most used operations in science and engineering, a lot of efforts for improving its efficiency have been made greatly. To accelerate such enormous computing, parallel processing architectures are mostly considered by decades. For the advance of manufacturing technology, high clock rate processors or multiple processors are also used to speed up the computation. In this thesis, another approach called merged arithmetic is included into our parallel architecture. It dissolves the boundary between the individual multipliers and adders to perform multiple multiply and addition in parallel. However, none of the methods which were presented previous for reducing partial product matrix is absolutely better than others. This study proposes a combined method to find out the most efficient reduction. Respecting the user’s demand is not the same all the time; our simulation results include three metrics, delay, cost, and delay × cost. Besides, the hardware interconnection for further implementation is also offered. It is very helpful for the design of such systems because a high performance throughput and low cost system are both what we concern.
論文摘要 i
Abstract ii
Contents iii
List of Figures v
List of Tables vi
1 Introduction 1
1.1 Background and Motivation 1
1.2 Related Work 2
1.3 About This Thesis 3
2 Matrix Multiplication 4
2.1 Matrix Multiplication 4
2.2 SIMD Matrix Multiplication 5
3 Former Work 8
3.1 Fast Multiplier 8
3.1.1 Wallace Tree 10
3.1.2 Dadda Tree 11
3.1.3 Fast Adder 13
3.2 2’s-Complement Multiplication 13
3.3 Merged Arithmetic 14
3.4 Fixed-Point Number System 19
4 Our Result 20
4.1 The Estimation Method 20
4.2 Simulation Results of the Previous Appraoches 21
4.3 Two Reduction Methonds on Demand 23
4.4 Our Result 26
4.5 An Improved Matrix Multiplier 28
5 Conclusion and Future Research 30
5.1 Concluding Remarks 30
5.2 Future Research 31
Bibliography 32
Appendix A 35
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