臺灣博碩士論文加值系統

本論文研究一0.18微米N型金屬氧化物半導體場效電晶體的模型建立並應用在3到5 GHz 超寬頻低雜訊放大器。研究標題分為兩個部份：
第一部份，我們可以藉由在射頻金屬氧化物半導體場效電晶體中，不同閘極寬度和閘極數量來觀察S參數、雜訊因子和功率效能。我們分析後可知當閘極寬度越大轉折效應會更明顯且閘極電阻越高轉折效應會往低頻移動，我們可由S11和S22觀察到轉折效應的移動。
在國家奈米實驗室量測完之後，我們必須使用準確的去嵌入方法來得到金屬氧化物半導體場效電晶體的本質部份，因為接觸墊和傳輸線會產生寄生效應來影響金屬氧化物半導體場效電晶體的本質量測資料。先前，我們使用開路去嵌入方法來萃取金屬氧化物半導體場效電晶體本質部份的S參數，但是得到的S參數在高頻中會有漂移的現象，原因是在高頻中使用開路去嵌入方法無法扣除ㄧ些寄生效應。因此，我們經由改良式三階段去嵌入方法可以得到金屬氧化物半導體場效電晶體本質部份的S參數並且完全扣除寄生效應的影響。最後，我們使用得到的S參數來建立金屬氧化物半導體場效電晶體小訊號模型，使用台灣積體電路公司的0.18微米製程技術，此技術包括BSIM3v3模型的直流特性、閘極串聯電阻、汲極串聯電阻以及汲極和矽基板間的寄生電阻。此外，我們也應用在台灣積體電路公司的0.35微米製程技術上並建立金屬氧化物半導體場效電晶體射頻大訊號模型，我們以台灣積體電路公司的BSIM3v3 HSPICE模型為基礎建構金屬氧化物半導體場效電晶體射頻大訊號模型可以到達20GHz.
第二部份，我們闡述一3到5GHz超寬頻低雜訊放大器使用台灣積體電路公司的0.18微米製程技術。我們使用串連電感補償方式來增加低雜訊放大器的增益和頻寬性能，一電阻並並回授藉由減少窄頻低雜訊放大器輸入的Q值和增益頻寬平坦，提供寬頻輸入匹配和降低雜訊。量測結果顯示電壓增益(Av)大於20dB，隔離係數(S12)低於-35dB，雜訊因子(NF)和輸入反射係數(S11)在5GHz前分別小於6dB和-9dB。晶片面積包括接觸墊為0.66平方微米，雜訊放大器的供應電壓為2.5伏特，供應電流為9.76 mA，功率消耗為24.4 mW。這結果可以幫助射頻積體電路工程師來實現一微型化接收器積體電路設計。

In the thesis, Modeling of 0.18 μm nMOSFETs is design and applications on the implementation of a 3-5 GHz UWB LNA. Research title have two parts：
In first part, we can observe the S parameter, RF noise figure and power performance influenced by the several kinds of width and gate finger in RF MOSFETs. We analysis that the width is increasing and the kink effect point is conscious obviously, the lower frequency of kink effect point, the higher gate resistance (Rg) value, our results show the kink phenomena in S11 and S22.
Then, after measure from NDL, we must use accurate de-embedding method to obtain intrinsic MOSFETs, because pad and transmission line will produce parasitic effect to influence on MOSFETs data which we want to take off. Previously, we use open de-embedding to extract S parameter of intrinsic MOSFETs, but S parameter will produce drift effect in high frequency after using open de-embedding method, because its method can not take off some intrinsic effect in high frequency. Hence, pass through improve three step de-embedding method, so we can obtain intrinsic MOSFETs and take off intrinsic effect clearly. Finally, we use S parameter of obtain intrinsic MOSFETs data to set up MOSFETs small-single models in TSMC 0.18 μm CMOS technology process which include intrinsic Bsim3v3 model for DC characteristics, series resistance of gate fingers, drain fingers and parasitic resistance between drain and silicon substrate. Furthermore, we can apply in the TSMC 0.35 μm technology process and set up its modeling, the construction of RF large-signal (and small-signal) model of TSMC 0.35 μm (and 0.18 μm) CMOS process. Based on the BSIM3v3 HSPICE model provided by TSMC, we construct scablable RF large-signal models of MOSFETs which can be applied up to 20 GHz.
In second part, we demonstrate a miniaturized UWB low noise amplifier is implemented in 0.18 μm CMOS technology process for a 3–5 GHz UWB system. We use inductive-series peaking technique was used to enhance the gain and bandwidth performances of the LNA. The resistive shunt-shunt feedback provides wideband input matching with small noise figure (NF) degradation by reducing the Q-factor of the narrow band LNA input and flattens the pass band gain. The measurement results show voltage gain greater than 20 dB, reverse isolation (S12) lower than 35 dB, and noise figure (NF) lower than 6 dB were achieved for frequencies lower than 5 GHz. In addition, input return loss (S11) lower than -9 dB was achieved for frequencies lower than 5 GHz. The chip area is only 0.66 mm2, excluding the test pads. This LNA drains 9.76 mA current at supply voltage of 2.5 V, i.e. it only consumes 24.4 mW power consumption. These results are helpful for RFIC designers to realize miniaturized receiver front-end ICs.

Chapter 1 Introduction 1
1.1 Motivation 2
1.2 Thesis Organization 4

Chapter 2 Source-to-Body and Drain-to-Body spacing on RF CMOS 7
2.1 Introduction 7
2.2 Device Architecture 9
2.3 Theory 10
2.4 Measurement Results 18
2.5 Conclusion 26

Chapter 3 MOSFETs Modeling for RF IC Design 27
3.1 Introduction 27
3.2 The Two-Port Network and the Representation of S Parameter 29
3.3 Pad in silicon and its effect 31
3.3.1 Wideband modeling of open dummy pad device 31
3.3.2 Pad structure 32
3.3.3 Pad parasitic effect and modify 33
3.3.4 Dummy Pad Measurement Result 34
3.4 Pad de-embedding in RF CMOS 37
3.4.1 Calibration and Measurement 37
3.4.2 Probe Pad Layout technique 38
3.4.3 Fitting Result of Pad Modeling 42
3.5 MOSFETs equivalent circuit model 44
3.6 Improved three-step de-embedding method to accurately account for MOSFETs 46
3.6.1 Calculation of Parasitic Elements 48
3.6.2 Model Assumptions and Improvements Compared to the Original Three-Step De-Embedding Method 51
3.6.3 De-embedding of S parameter 52
3.7 Noise in MOSFETs 54
3.8 Measurement Results and Discussions 56
3.9 MOSFETs Modeling Extraction 61
3.10 Conclusion 68

Chapter 4 High-Coupling Factor Interlaced-Stacked Transformers with Various Turn Ratio for RFIC Applications 69
4.1 Introduction 69
4.2 Monolithic Transformer 70
4.2.1 Basic Principle 72
4.2.2 Transformer Structure 74
4.2.3 Transformer Parameters Extraction 76
4.3 Measurement Results and Discussions 83
4.4 Transformer Modeling Extraction 89
4.4.1 Fitting Result of Modeling 91
4.5 Conclusion 94
Chapter 5 Ultra Wideband Low Noise Amplifier 95
5.1 Introduction 95
5.1.1 UWB Technology 96
5.1.2 UWB Applications 98
5.2 Feedback Topology 99
5.3 Bandwidth Enhancement with Inductive Peaking and Zero Peaking Technique 103
5.4 Basic Concepts and Specifications of LNA 109
5.4.1 Noise 109
5.4.2 Intermodulation 110
5.4.3 Sensitivity and Dynamic Range 112
5.5 Circuit Design for 3~5 GHz Ultra Wideband LNA 114
5.5.1 Circuit design 116
5.5.2 Measurement Results and Discussions 120
5.6 Conclusion 124

Chapter 6 Conclusion 125

References 127
Appendix 131
Publication List 136

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Chapter 3
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Chapter 4
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Chapter 5
[37]Ultra-wideband (UWB Technology) of Enabling high-speed wireless person area networks http://www.intel.com/technology/comms/uwb/
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Appendix

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