臺灣博碩士論文加值系統

時脈資料回復電路應用於數位通訊系統接收器中，是一個重要的元件，其應用涵蓋了許多需要點對點序列傳輸的數位系統，如光纖網路規格中的非同步傳輸模式 (ATM)、同步光纖網路(SONET)、同步數位階層(SDH)、光纖分散式資料介面(FDDI)、乙太網路(Ethernet)、波多分工技術(WDM)、高密度波多分工技術(DWDM)等，以及個人電腦與外接周邊產品的通用序列埠（USB）介面。近幾年，為了減少排線數量及功率消耗，在個人電腦內部介面的發展也由傳統的並列傳輸方式，演進至目前的高速串列傳輸，如Serial-ATA、PCI-Express等。

在本論文中，使用0.35μm製程設計出一個能夠在低電壓操作的時脈資料回復電路，電路整體架構設計採用鎖相迴路概念，相位頻率偵測器的輸入端採全差動架構以利低電壓操作；論文中亦提出了一個改良的壓控震盪器，可以對頻率-電壓特性曲線的線性度作有效的改善，且降低了增益和雜訊敏感度；此電路是採用TSMC0.35μm 2P4M製程實現，操作頻率1 GHz，在壓控震盪器方面的量測結果得到頻率範圍從900 MHz到1160 MHz，峰對峰值及均方根值抖動分別為11.64 ps和1.36 ps，在中心頻率1 MHz附近的相位雜訊為-110.4 MHz，功率消耗為32.5 mW；在時脈資料回復電路的量測結果得到的峰對峰值及均方根值抖動分別為348.26 ps和58.04 ps，在電源電壓為1.8伏特時，消耗功率為37.7 mW；包含測試電路及開回路壓控震盪器時，整個晶片面積為1520×914 μm2。

Clock and data recovery circuit is an important component in digital communication systems. The applications include many point-to-point digital transmission systems, such as Asynchronous Transfer Mode (ATM), Synchronous Optical Network (SONET), Synchronous Digital Hierarchy (SDH), Fiber Distributed Data Interface (FDDI), Ethernet, Wavelength Division Multiplexing (WDM), Dense Wavelength Division Multiplexing (DWDM) and interface of universal serial bus (USB) between personal computer and external device. In recent years, the high-speed serial link has also encroached on the board level as a standard interface of host computer to reduce the transmission line and power consumption, such as serial-ATA and PCI-express.

In the thesis, a low-voltage clock and data recovery circuit with PLL-based topology in 0.35μm process. Phase and frequency detector adopts differential scheme for low-voltage operation. In addition, a modified voltage-controlled oscillator is proposed to improve linearity of frequency-voltage characteristic curve and reduce gain and noise sensitivity. The circuits are implemented in TSMC 0.35μm 2P4M and operating frequency is 1 GHz. The measured tuning range of improved VCO is from 900 MHz to 1160 MHz at 1 GHz, peak-to-peak and root-mean-square jitter are 11.64ps and 1.36ps, respectively. The measured phase noise is -110.4 dBc/Hz at 1-MHz offset from a 1.005-GHz center frequency. Power consumption is 32.5 mW. The measured peak-to-peak and root-mean-square jitter of the clock and data recovery under 1.8 V are 348.27 ps and 58.05 ps, respectively. Power consumption is 37.7 mW. The chip area included test circuits and pads is 1520×914 μm2.

Acknowledgements
Abstract(Chinese)................................................. I
Abstract(English)................................................. II
Table of Contents................................................. IV
List of Figures................................................... VI

Chapter 1 Introduction...................................................... 1
1.1 Motivation.................................................... 1
1.2 Background.................................................... 3
1.3 Thesis Organization........................................... 5

Chapter 2 Overview of Clock and Data Recovery..................... 6
2.1 Basic Concepts................................................ 6
2.1.1 Properties of Random Binary Data............................ 6
2.1.2 Data Formats................................................ 8
2.1.3 Eye Pattern................................................. 10
2.1.4 Inter-Symbol Interference................................... 11
2.2 The Evolution and Architectures of CDR........................ 13
2.2.1 Evolution................................................... 13
2.2.2 Classification by Sampling Scheme........................... 17
2.2.3 Classification by Operation Frequency....................... 19
2.2.4 Classification by Loop Quantities........................... 19
2.2.5 Classification by External Reference Frequency.............. 19
2.3 Phase Detector for Random Data................................ 21
2.3.1 Introduction................................................ 21
2.3.2 Hogge Phase Detector........................................ 22
2.3.3 Alexander Phase Detector.................................... 22
2.3.4 Half-Rate Phase Detector.................................... 24
2.4 Characteristics of Jitter..................................... 26
2.4.1 Jitter Definition........................................... 26
2.4.2 Jitter Components........................................... 27
2.4.3 Jitter Measurement.......................................... 30
2.4.4 Jitter in Closed Loop....................................... 33

Chapter 3 Design for a Low-Voltage Clock and Data Recovery........ 35
3.1 Design Consideration.......................................... 35
3.2 Design of Improved Voltage-Controlled Oscillator.............. 37
3.2.1 Original Topology........................................... 38
3.2.2 An Improved Voltage-Controlled Oscillator................... 40
3.3 Design of Modified Phase-and-Frequency Detector............... 43
3.4 Design of Charge-Pump and Loop-Filter......................... 47
3.5 Design of Decision Circuit.................................... 53
3.6 Circuits for Testing.......................................... 53
3.6.1 Pseudo-Random Bit Sequence.................................. 54
3.6.2 Phase-Locked Loop........................................... 58

Chapter 4 Test Setup and Experimental Results..................... 59
4.1 Test Setup.................................................... 59
4.1.1 Introduction................................................ 59
4.1.2 Input Source................................................ 60
4.1.3 Power Supply and Ground..................................... 61
4.1.4 Board Plan.................................................. 63
4.2 Experimental Results.......................................... 67
4.2.1 Introduction................................................ 67
4.2.2 Phase-locked loop........................................... 68
4.2.3 Improved Voltage-Controlled Oscillator...................... 68
4.2.4 Clock and Data Recovery..................................... 71

Chapter 5 Conclusion.............................................. 73

Reference......................................................... 75

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