臺灣博碩士論文加值系統

本論文以超寬頻(Ultra-wideband)低雜訊放大器和ka頻段低雜訊放大器為研究目標，研究主題分成兩部分：
第一部份為應用於接收端超寬頻系統之3.1~10.6 GHz低雜訊放大器。主要設計了兩種類型之低雜訊放大器，皆利用電阻負回授技巧，並配合Inductive peaking技術來增加主極點頻率，進而擴展3 dB頻寬。
一種為使用二級共射放大器，其中第二級是由達靈頓對所組成，利用達靈頓的兩倍截止頻率特性達到高電流增益，並配合多組電阻負回授達成頻寬擴展；在此以TSMC35 SiGe BiCMOS完成了三組低雜訊放大器依序分別為多個電感配合多組電阻負回授方式、使用全電阻方式和僅使用一顆電感配合多組電阻負回授方式。實驗結果顯示：第一組放大器，3 dB頻寬可達17 GHz，在頻段3.1~10.6 GHz，S21皆維持8±0.5 dB的增益，輸入、輸出反回損耗皆小於-9 dB，以及最低雜訊指數為3.6 dB，此電路消耗之功率為21 mW。第二組放大器在3.1~10.6 GHz頻率下有著最高增益S21為16.2 dB，輸入反回損耗低於-12 dB，輸出反回損耗低於-18 dB，以及雜訊指數為3.8~6.2 dB，此電路消耗之功率為40.7 mW。第三組放大器在3.1~10.6 GHz頻率下有著最高增益S21為12.16 dB，輸入反回損耗低於-6.36 dB，輸出反回損耗低於-13.9 dB，以及雜訊指數為3.5~5.6 dB，此電路消耗之功率為19.2 mW。
另一種電路為僅採用兩級Cascade common-source的架構，在每一級使用local feedback電阻回授方式來達成，並於第二級之輸入端加入一個電感，做為peaking的功用。在此分別使用TSMC18 CMOS和TSMC35 SiGe BiCMOS來實現。在使用TSMC18 CMOS所完成的2-7 GHz LNA中，輸入反回損耗為-10.4 ~ -15.3 dB，輸出反回損耗為-19.4 ~ -10.3 dB，增益S21為9 ~ 8 dB，以及雜訊指數為4.86 ~ 4.47 dB，此電路僅消耗15.6 mW功率。另一個使用TSMC35 SiGe BiCMOS所完成的3.1-10.6 GHz LNA，其量測結果：輸入反回損耗為-14.8 ~ -31.7 dB，輸出反回損耗為-24.9 ~ -13.2 dB，增益S21為7.6 ~ 6 dB以及雜訊指數為3.9 ~ 5.8 dB，此電路消耗功率為23.25 mW。
第二部份為設計一適用於Ka頻段和毫米波之低雜訊放大器。我使用三級cascaded common-source架構以TSMC CMOS 0.18 m和JAZZ SiGe 0.18 m分別實現了32 GHz 、60 GHz的低雜訊放大器。在32 GHz的低雜訊放大器中，實驗結果顯示：在31.5 GHz頻率下有著最高增益S21為10.35 dB，在頻率31.5 GHz有著最小輸入反回損耗-15.7 dB，在頻率33 GHz有著輸出反回損耗低於-16.1 dB，此外電路消耗之功率為27 mW。而在60 GHz的低雜訊放大器，僅完成模擬，並委託國外進行佈局、下線。


關鍵詞：低雜訊放大器、超寬頻低雜訊放大器、Ka-band低雜訊放大器、達靈頓對、電感補償、電阻負回授

This thesis aim is to design an ultra wideband low noise amplifier and Ka-band low noise amplifier. Study the theme be divided into two parts：
In first part, 3.1 ~ 10.6 GHz low noise amplifier is designed for ultra wideband (UWB). The mainly two types of low noise amplifier were added multiple feedback loops and inductive peaking technique to enhance the frequency of the dominant pole and then expand 3 dB bandwidth of the LNA.
One is using two-stage common emitter whose the second stage is Darlington pair consisting. We employ the double cut-off frequency characteristic of Darlington pair to achieve high current gain and added multiple negative feedback resistors to expand bandwidth. The three types of low noise amplifier are implemented in 0.35 m SiGe BiCMOS, these are multiple inductors with multiple resistors negative feedback, inductorless and only one inductor with multiple resistors negative feedback, respectively. The first type of the amplifier, measured results show that the 3dB bandwidth is 17 GHz, the power gain (S21) of 8 dB, input return loss (S11) and output return loss (S22) below -9 dB and minimum noise figure of 3.6 dB over 3.1-10.6 GHz while consuming 21 mW. The second type of the amplifier measured results show the power gain (S21) of 16.2 dB, input return loss (S11) below -12 dB, output return loss (S22) below -18 dB and noise figure of 3.8 ~ 6.2 dB form 3.1 to 10.6 GHz. The total power consumption is 40.7 mW. The third type of the amplifier, measured results show the maximum power gain (S21) of 12.16 dB. The input return loss (S11) is less than -6.36 dB, output return loss (S22) below -13.9 dB and minimum noise figure of 3.5 ~ 5.6 dB over 3.1-10.6 GHz while consuming 19.2 mW.
The other is Cascade common-source structure. We used local resistor feedback and added peaking inductor on gate (base) of second stage to increase 3 dB bandwidth. The circuit is fabricated in standard 0.18 m CMOS process and 0.35 m SiGe BiCMOS technology, respectively. In standard 0.18 m CMOS process LNA, the measured results are S11 of -10.4 ~ -15.3 dB, S22 of -19.4 ~ -10.3 dB, S21 of 9 ~ 8 dB, and NF of 4.86 ~ 4.47 dB from 2 to 7 GHz. The total power consumption is only 15.6 mW at +1.5 V supply voltage. The other using 0.35 m SiGe BiCMOS technology, the measured results are S11 of -14.8 ~ -31.7 dB, S22 of -24.9 ~ -13.2 dB, S21 of 7.6 ~ 6 dB and NF of 3.9 ~ 5.8 dB from 3.1 to 10.6 GHz. The total power consumption is 23.25 mW at +2.7v and +1.5v supply voltage.
The last part, we design Ka-band and millimeter-wave low noise amplifier. The three stage cascaded common-source structure is implemented in standard 0.18 m CMOS technology and JAZZ 0.18 m SiGe BiCMOS technology to achieve 32 GHz and 60 GHz, respectively. The measured results of the Ka-band show the highest power gain (S21) is 10.35 dB at 31.5 GHz, minimum input return loss (S11) of -15.7 dB at 31.5 GHz and minimum output return loss (S22) of -16.1 dB at 33 GHz. The total power consumption is only 27 mW. In addition, the 60 GHz LNA also are designed and the only results of simulation are presented.

Keywords: low noise amplifier, ultra wideband, Ka-band low noise amplifier, Darlington pair, inductive peaking, resistors negative feedback

Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Thesis Overview 2

Chapter 2 RF Fundamentals and Ultra-Wideband System
Overview 4
2.1 RF Fundamentals 4
2.1.1 S-Parameters 4
2.1.2 Noise in Transistors 6
2.1.3 Noise Figure 9
2.1.4 Intermodulation 11
2.1.5 Gain Compression 14
2.1.6 Sensitivity and Dynamic Range 15
2.2 A brief introduction of UWB 16

Chapter 3 A 3.1 to 10.6 GHz Ultra-Wideband LNA Using
Darlington Pair 20
3.1 Principle of the circuit design 21
3.2 Input Matching Principle 22
3.3 UWB Gain Flatness Technique 23
3.4 Chip Implementation and Measurement Result 25
3.5 Improved UWB LNA 30
3.6 Simulation and Measurement Results 33
3.7 Conclusions 41

Chapter 4 Cascaded Two-Stage Amplifier with a Peaking
Inductor for UWB System 42
4.1 Principle of the circuit design 42
4.2 Input Matching Principle 44
4.3 UWB Gain Flatness Technique 44
4.4 Simulation and Measurement Results 46
4.5 Similar amplifier using SiGe BiCMOS Technology 51
4.6 Simulation and Measurement Results 52
4.7 Conclusions 57

Chapter 5 A Ka-Band Low Noise Amplifier Using Standard
0.18 mm CMOS Technology 58
5.1 Principle of the circuit design 59
5.2 Simulation and Measurement Results 62
5.3 An Analysis of Silicon Substrate Effects in 60GHz LNA 66
5.4 Simulation Results of 60GHz 70
5.5 Conclusions 74

Chapter 6 Conclusions 75
References 77
Publication List 80
Appendix 81

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