(3.238.174.50) 您好!臺灣時間:2021/04/17 03:34
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果

詳目顯示:::

我願授權國圖
: 
twitterline
研究生:雷穎
研究生(外文):Ying Lei
論文名稱:應用於語音辨識之梅爾倒頻譜參數超大型積體電路設計
論文名稱(外文):Chip Design of Mel Frequency Cepstral Coefficient for Speech Recognition
指導教授:吳俊德吳俊德引用關係
指導教授(外文):Gin-Der Wu
學位類別:碩士
校院名稱:國立暨南國際大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2006
畢業學年度:94
語文別:英文
論文頁數:50
中文關鍵詞:快速傅立葉轉換梅爾倒頻譜參數
外文關鍵詞:fast fourier transform (FFT)Mel-scale frequency cepstral coefficient (MFCC)
相關次數:
  • 被引用被引用:0
  • 點閱點閱:237
  • 評分評分:系統版面圖檔系統版面圖檔系統版面圖檔系統版面圖檔系統版面圖檔
  • 下載下載:84
  • 收藏至我的研究室書目清單書目收藏:0
本篇論文提出兩顆可以應用於多媒體系統的語音信號辨識的晶片。這個系統主要包含個主要的部份,分別是快速傅立葉轉換(fast fourier transform)處理器、梅爾倒頻譜參數(Mel-scale frequency cepstral coefficient)擷取晶片以及算數邏輯運算單元(ALU)架構的數位信號處理器。其中數位信號處理器已經被之前的學長所實現,在這篇論文,我們主要的貢獻為快速傅立葉轉換處理器以及梅爾倒頻譜參數擷取晶片。在快速傅立葉轉換處理器的設計上,為了降低晶片的功率消耗以及計算量,我們採用一種新的暫存器陣列方法並使用二維管線式的架構來設計。在梅爾倒頻譜參數擷取晶片的設計上,我們採用雙累加暫存器的架構來降低計算量,另外縮小了對數的查表表格大小,而且利用限制計時器(gating clock)的方法來降低晶片的功率消耗。應用TSMC 0.18um 標準單元(standard cell)合成出處理器電路,FFT/IFFT處理器晶片面積約為4.73mm2 ,MFCC晶片面積約為1.71mm2 ,工作頻率都為100MHz。
This paper proposed the chip design of speech recognition for multimedia system. It is composed by three cores: a low-power high performance fast fourier transform (FFT) processor, a Mel-scale frequency cepstral coefficient (MFCC) circuit, and a dual-ALU digital signal process (DSP) processor with dynamic time warping speech recognition algorithm. The DSP processor had been implemented by previous researcher. In this paper, we mainly proposed the FFT processor and MFCC chip. In the FFT processor, we proposed a novel register array based pipelined radix-2 structure to reduce power consumption and computation cycles. In the MFCC circuit, we adopt one pair of accumulation procedure to reduce the computation of Mel frequency bank. In addition, we also minimize the look-up table size for logarithm operations, and we use gating clock issue to reduce power consumption. The two chips are synthesized by TSMC 0.18um cell library. The die size of the FFT/IFFT processor is approximately 4.73 . And the die size of the MFCC chip is approximately 1.71 . The two chips both work at 100 MHz.
Chinese abstract i
English abstract ii
Contents iii
List of tables v
List of figures vi

1. Introduction 1
1.1 Preview of the FFT/IFFT processor 1
1.2 Preview of the MFCC chip 4
1.3 Preview of the DSP processor 6
1.4 Preview of our proposed dual-ALU DSP processor 7
2. DTW algorithm 15
3. Overview of the System 18
4. Chip design of FFT/IFFT 20
4.1 Hardware architecture of the butterfly unit 21
4.2 Hardware architecture of the register array 23
4.3 Hardware architecture of the address generator 25
4.4 Overview of the FFT/IFFT processor 28
5. Chip design of MFC 31
5.1 Hardware architecture of the Mel frequency bank unit 33
5.2 Hardware architecture of the DCT unit 36
5.3 Hardware architecture of the logarithm unit 38
5.4 Overview of MFCC circuit 40
6. Analysis 42
7. Conclusion 47

Bibliography 48
Bibliography
[1]L. R. Rabiner and B. Gold, “Theory and Application of Digital Processing.” Prentice-Hall, Inc, 1975.
[2]E. H. Wold and A. M. Despain, “Pipeline and parallel-pipeline FFT Processor for VLSI Implementation,” IEEE Trans.Comput., C-33(5):414-426, May, 1984.
[3]M. B. Bevan, “A Low-Power, High-Performance,1024-point FFT Processor,” IEEE Journal of Solid-State Circuits, vol. 34, no. 3, pp. 380-387, March, 1999.
[4]L. Jia, Y. Gao, J. Isoaho, and H. Tenhunen, “Implementation of a low power 128-point FFT Processor,” in Proceedings of Fifth International conference on Solid-State and Integrated Circuit Technology, pp. 369-372, 1998.
[5]K. S. Stevens and B. W. Suter, “A mathematical approach to a low power FFT Architecture,” in Proc. IEEE International Symposium on Circuits and Systems, pp. II-21-II-24, 1998.
[6]M. Hasan, T. Arslan, and J. S. Thompson, “A delay spread based low power reconfigurable FFT processor architecture for wireless receiver,” IEEE International Symposium on System-on-Chip, pp. 135-138, 2003.
[7]Yutian Zhao, Ahmet T. Erdogan, and Tughrul Arslan, “A Low-Power and Domain-Specific Reconfigurable FFT Fabric for System-on-Chip Applications,” IEEE International Symposium on Parallel and Distributed, pp. 169a-169a, April, Nov. 2005.
[8] O. Burak, Tuzun, M. Demirekler, and K. Bora, “Comparison of Parametric and Non-Parametric Representations of Speech for Recognition,” Proceedings of MELECON, Mediterranean Electrotechnical Conference, 1994, pp.65-68.
[9] Jia-Ching Wang, Jhing-Fa Wang, and Yu-Sheng Weng, “Chip Design of Mel Frequency Cepstrum Coefficient for Speech Recognition,” IEEE Trans. Acoustics, Speech, and Signal Processing, vol. 6, pp. 3658-3661, June 2000.
[10] Bin-Da Liu and Hsin-Hung Lin, “Implementation of MFCC Processor Design for Speech Feature Extraction,” Master Thesis, National Cheng Kung University, Taiwan, R.O.C., June 2001.
[11] H. Sakoe and S. Chiba, “Dynamic programming algorithm optimization for spoken word recognition,” IEEE Trans. Acoustics, Speech, and Signal Processing, vol. 26. pp. 43-49, Feb 1978.
[12] Harvey F. Silverman and David P. Morgan, “The application of dynamic programming to connected speech recognition,” IEEE ASSP Magazine, vol. 7, pp. 6-25, July 1990.
[13] L. Rabiner, A. Rosenberg, and S. Levinson, “Conderations in dynamic time warping algorithms for discrete word recognition” IEEE Trans. Acoustics, Speech, and Signal Processing, vol. 26. pp. 575-582, Dec 1978.
[14] H. Hassler and N. Takagi, “Function Evalution by Table Look-up and Address,” Proceeding of the 12th Symposium on Computer Arithmetic, pp. 10-16.
[15] Amphion, CS2410 8-1024 Point FFT/IFFT, Jul. 2001.
[16] M. Wosnitza, M. Cavadini, M. Thaler, and G. TrÖster, “A High precision 1024-point FFT processor for 2D convolution,” in Proc. IEEE Int. Solid-State Circuits Conference, vol. 41, pp. 118-119, 424, 1998.
[17] Drey Enterprise Inc., Jaguar II Variable-Point (8-1024) FFT/IFFT Specification, 1998.
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top
系統版面圖檔 系統版面圖檔