臺灣博碩士論文加值系統

本論文是一個應用於SONET OC-48的時脈與資料回復電路(Clock and Data Recovery Circuit,簡稱CDR電路)，電路主要應用於光纖通訊的接收器端，電路功能是將接收器所接收到的雜亂訊號，加以回復並萃取出其資料的時脈訊號。由於目前CDR電路的相位偵測器一直都是造成電路震盪器頻率抖動的因素之一，所以針對此缺點我想出了一個適用於OC-48規格的相位偵測器，採取串列式取樣，穩態時大幅降低震盪器的抖動。電路是使用TSMC 1.8V 0.18μm 1P6M18 CMOS製程，面積大小為0.878 mm × 0.739 mm，電路整體功耗為51.58mW (包含輸出緩衝器)，回復時脈的相位雜訊為-93dBc/Hz at 1MHz Offset。

The topic of this thesis is a clock and data recovery circuit for SONET-OC48 application. Mainly applies in the optical fiber communication receiver. The function of CDR circuit is that it extracts clock from noisy input random data and retims the data. Because the present CDR circuit phase detector continuously all creates one of CDR circuit oscillator frequency vibration factors. To alleviate the problem, I propose a new phase detector with cascade sampling technique.When CDR is in the lock condition, the phase detector doesn’t provide any singal to influence VCO frequency. That could get a better BER performance.
The Chip, whose size is 0.878 mm × 0.739 mm, is realized by TSMC 0.18μm 1P6M18 CMOS process using 1.8V. The chip including output buffer dissipates 51.58mW. Retimed clock phase noise is measured to be -93dBc/Hz at 1MHz Offset .

致謝
中文摘要...................................................................................................... Ⅰ
英文摘要...................................................................................................... Ⅱ
目錄............................................................................................................. Ⅲ
圖目錄...........................................................................................................Ⅴ
表目錄...........................................................................................................Ⅸ


Abstract
第一章 簡介............................................................................................1
1-1 研究動機..................................................................................1
1-2 先前文獻探討............................................................................3
1-3 論文大綱..................................................................................5
第二章 時脈與資料回復電路.....................................................................6
2-1 CDR電路架構簡介.....................................................................6
2-1-1 雙迴圈CDR電路............................................................7
2-1-2 無參考時脈雙迴圈CDR電路............................................8
2-1-3 雙VCO架構雙迴圈CDR電路..........................................9
2-1-4 超取樣CDR電路.............................................................10
2-2 相位偵測器的分析與演進..........................................................11
2-2-1 Hogge相位偵測器.........................................................11
2-2-1-1 Ｍodify Hogge 相位偵測器........................................13
2-2-1-2半速型 Hogge相位偵測器........................................14
2-2-2 線性取樣保持相位偵測器...............................................15
2-2-3-1 Alexander相位偵測器....................................................16
2-2-3-2 半速型Alexander相位偵測器....................................18
2-2-3-3 CML Latch架構半速型Alexander相位偵測器..............19
2-2-3-4 四分之一速率型相位偵測器.......................................20
2-2-4 八分之一速率型相位偵測器............................................20
2-3 資料格式..................................................................................22
2-3-1 NRZ資料and RZ資料...................................................22
2-3-2 亂數資料產生器電路.....................................................24
2-3-3 Intersymbol Interference(ISI)...........................................26
2-3-4 眼圖............................................................................26
2-3-5 Long-run.......................................................................28
2-4 抖動分析.................................................................................28
2-4-1 抖動轉換函數...............................................................29
2-4-2 抖動產生......................................................................32
2-4-3 抖動容忍度...................................................................34
2-5 位元錯誤率..............................................................................37
2-6 相位雜訊.................................................................................39
2-7 傳輸線....................................................................................41
第三章 OC-48時脈與資料回復電路之設計與實現......................................42
3-1 相關文獻討論.......................................................................... 42
3-2 電路設計.................................................................................44
3-2-1 預先放大器..................................................................44
3-2-2 數位式頻率偵測器........................................................45
3-2-3 相位偵測器..................................................................48
3-2-4 ΔT延遲時間產生電路...................................................52
3-2-5 震盪器.........................................................................54
3-2-6 充電泵電路...................................................................55
3-2-7 低通濾波器...................................................................56
3-3 迴路穩定度分析......................................................................58
3-4 模擬結果................................................................................61
第四章 量測方法與量測結果....................................................................68
4-1 量測考量....................................................................................68
4-2 量測方法....................................................................................69
4-3 量測結果....................................................................................72
第五章 結論...........................................................................................77

參考文獻..................................................................................................78

附錄 微帶線阻抗計算方法............................................................................. 80

參考文獻


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