臺灣博碩士論文加值系統

論文名稱：參考接地電壓之低電壓差動訊號傳輸介面設計與實現
校院系：國立暨南國際大學電機系 頁數：87頁
畢業時間：中華民國九十五年七月 學位別：碩士
研究生：董柏彣 指導教授：許孟烈 博士

摘 要

現今市面上各類多媒體與通訊產品需要快速的傳輸大量影音資料，產品之間資料傳輸介面要求的速度與傳輸資料量也因應提升。為了達到高速傳輸目的且不造成空間和功率的浪費，有許多高速串列傳輸介面被提出來，如低電壓差動訊號(LVDS)傳輸技術，它採用低電壓擺幅差動訊號來傳送串列資料，擁有高速作業、低功率消耗和提高抗雜訊干擾能力的特性。近年來更有採用參考接地電壓之低電壓差動訊號(GLVDS)傳輸方式來設計輸入輸出介面，它除了具有LVDS的高速、低雜訊干擾特性外，更能進一步減少功率消耗。
本論文主要是利用參考接地電壓之低電壓差動訊號(GLVDS)技術來設計操作於1Gb/s的低功率傳輸器與接收器，採用TSMC 1.8V 0.18μm 1P6M CMOS製程進行雛型晶片設計與下線製作，在傳輸線長度為55cm的情況下，模擬結果顯示傳輸器與接收器的傳輸速度可達1Gb/s，傳輸器功率消耗為2.7mW，接收器功率消耗為7.4mW。晶片大小為920μm*920μm，傳輸器為30μm*35μm，接收器為70μm*45μm。量測結果顯示晶片可正常工作在1Gb/s。

Title of Thesis: Design and Implementation for GLVDS I/O Interface
Name of Institute: Department of Electrical Engineering National Chi Nan University Pages: 87
Graduation Time: 2006/7 Degree Conferred: Master
Student Name: Bo-Wen Don Advisor Name: Meng-Lieh Sheu

Abstract

Nowadays, to transfer huge amounts of audio and video data in high speed for most kinds of multimedia and communication products in the market, the data transmission interface between products must have a large bandwidth. To achieve the required bandwidth without wasting space and power, plenty of high-speed serial interfaces have been developed, like Low Voltage Differential Signal (LVDS) technology. LVDS uses differential signal of low voltage swing to transfer serial data. It possesses a great number of properties, like high speed data throughput, low power dissipation and high noise immunity. In recent years, Ground referenced Low Voltage Differential Signal (GLVDS) technology has been proposed to design I/O interface. Not only does it have high speed and low noise interference properties, but also can save power dissipation further.
This thesis mainly utilizes Ground referenced Low Voltage Differential Signal (GLVDS) technology to design 1Gb/s low power transmitter and receiver. An experimental chip is designed and taped out by using TSMC 1.8V 0.18μm 1P6M CMOS process. The simulation results reveal that the transmission speed of the transmitter and the receiver can achieve 1Gb/s when transmission line is 55-cm. The power consumptions of the transmitter and the receiver are 2.7mW and 7.4mW, respectively. The chip area is 920×920μm2, where the transmitter size is 30×35μm2, and the receiver is 70×45μm2. The measurement results show that the chip can operate functionally at 1Gb/s.

目 錄
致謝
中文摘要.................................................... Ⅰ
英文摘要.................................................... Ⅱ
目錄........................................................ Ⅳ
圖目錄...................................................... Ⅵ
表目錄...................................................... Ⅹ

第一章 緒論................................................ 1
1.1 研究動機.......................................... 1
1.2 研究背景.......................................... 3
1.3 論文組織架構...................................... 13

第二章 參考接地電壓之低電壓差動訊號(GLVDS)規格與架構...... 14
2.1 低電壓差動訊號(LVDS)原理與規格簡介................ 15
2.1.1 LVDS原理、規格與優點.................... 15
2.1.2 RSDS簡介................................ 19
2.2 參考接地電壓之低電壓差動訊號(GLVDS)介紹.......... 21
2.2.1 GLVDS規格.............................. 21
2.2.2 GLVDS優點.............................. 22
2.2.3 GLVDS介面架構與原理.................... 25
2.3 傳輸品質分析...................................... 26

第三章 1Gb/s GLVDS傳輸器與接收器電路設計.................. 29
3.1 GLVDS傳輸器電路設計............................. 30
3.1.1 GLVDS傳輸器電路........................ 30
3.1.2 單端轉雙端電路........................... 31
3.1.3 亂數產生器電路........................... 31
3.1.4 壓控振盪器電路........................... 32
3.2 GLVDS接收器電路設計............................. 35
3.3 模擬結果.......................................... 36

第四章 晶片製作及量測結果.................................. 50

第五章 結論................................................ 65

參考文獻.................................................... 67
附錄A 1GHz鎖相迴路(Phase Lock Loop)設計................... 70
附錄.1 鎖相迴路架構分析.................................. 71
附錄.2 鎖相迴路架構...................................... 73
附錄.2.1 相位頻率檢測器........................... 73
附錄.2.2 電荷幫浦與迴路濾波器..................... 75
附錄.2.3 電壓控制振盪器........................... 77
附錄.2.4 除頻器................................... 78
附錄.3 模擬結果.......................................... 79

附錄B HSPICE 傳輸線模型.................................. 85

附錄C Package 模型........................................ 87


























圖 目 錄
圖1-1 數種I/O介面規格[1]............................... 2
圖1-2 傳輸器電路圖[4].................................. 3
圖1-3 接收器電路圖[4].................................. 3
圖1-4 傳輸器架構圖[5].................................. 4
圖1-5(a) 互補的自我偏壓差動放大器(CSDA)[5] 4
圖1-5(b) 主動負載差動放大器(ALDA)[5]..................... 4
圖1-5(c) 大共模範圍的差動放大器(VCDA)[5]................. 5
圖1-6(a) 接收器架構[5].................................... 5
圖1-6(b) 接收器內部電路[5]................................ 5
圖1-7 傳輸器電路架構[6]................................ 6
圖1-8(a) 接收器電路架構[7]................................ 7
圖1-8(b) 接收器內部電路[7]................................ 7
圖1-8(c) 共模電壓準位轉移電路[7].......................... 7
圖1-9(a) 傳輸器架構圖[8].................................. 9
圖1-9(b) 傳輸器電路[8].................................... 9
圖1-10(a) 傳輸器架構圖[8].................................. 9
圖1-10(b) 傳輸器電路圖[8].................................. 10
圖1-11(a) 接收器架構圖[9].................................. 11
圖1-11(b) 電流選擇器[9].................................... 11
圖1-12 GLVDS電路圖[1]................................. 12
圖2-1 傳輸器輸出訊號擺幅示意圖[2]...................... 18
圖2-2 典型LVDS系統................................... 18
圖2-3 LVDS基本架構................................... 18
圖2-4 LVDS傳送邏輯1.................................. 19
圖2-5 LVDS傳送邏輯0.................................. 19
圖2-6 RSDS應用於平面顯示器系統[3]..................... 20
圖2-7 RSDS介面架構[3]................................. 21
圖2-8 接收器敏感度測試[16]............................. 23
圖2-9 接收器共模電壓範圍[16]........................... 24
圖2-10 接地準位偏移測試[16]............................. 24
圖2-11 GLVDS典型的介面架構........................... 25
圖2-12 Jitter分類圖[25]................................... 27
圖2-13 眼圖的形成[26]................................... 27
圖2-14 眼圖參數定義[27]................................. 28
圖2-15 眼圖遮罩[27]..................................... 28
圖2-16 Bathtub Curve[28].................................. 28
圖3-1 參考接地電壓之低電壓差動訊號(GLVDS)傳輸器與接收器測試架構圖.....................................
30
圖3-2 參考接地電壓之低電壓差動訊號(GLVDS)傳輸器電路圖...............................................
33
圖3-3 資料為邏輯1時的等效電路圖....................... 33
圖3-4 單端轉雙端數位邏輯圖............................. 34
圖3-5 PRBS電路架構圖(7級)............................. 34
圖3-6 TSPC電路架構圖.................................. 34
圖3-7 四級環形振盪器電路結構圖......................... 35
圖3-8 單位延遲電路圖................................... 35
圖3-9 參考接地電壓之低電壓差動訊號(GLVDS)接收器電路圖 36
圖3-10 VCO的調諧範圍.................................. 37
圖3-11 VCO的輸出波形.................................. 38
圖3-12 VCO做post-simulation後得到的調諧範圍............. 38
圖3-13 掛負載電容(0.012pF)所得VCO之調諧範圍............ 39
圖3-14 PRBS輸出之亂數資料.............................. 40
圖3-15 PRBS輸出127 bits亂數資料......................... 40
圖3-16 PRBS電路做post-simulation所得結果................. 41
圖3-17 單端轉雙端產生之互補訊號......................... 41
圖3-18 觀察互補訊號的延遲時間........................... 42
圖3-19 單端轉雙端電路做post-simulation所得結果............ 42
圖3-20 訊號經傳輸器(Transmitter)轉換波形.................. 43
圖3-21 接收器(receiver)接收到訊號......................... 43
圖3-22 觀察傳輸器輸出電流............................... 44
圖3-23 M5、M6、M7和M8之閘極端電壓變化............... 44
圖3-24 接收器(receiver)M5和M6電流變化................... 45
圖3-25 接收器(receiver)還原訊號........................... 45
圖3-26 接收器還原資料之眼圖............................. 46
圖3-27 整體電路在不同corners下所得結果.................. 46
圖3-28 不同傳輸率下所能傳送的最長距離................... 47
圖3-29 整體電路之post-simulation結果...................... 47
圖3-30 接收器還原訊號(訊號源為PLL)...................... 48
圖3-31 接收器還原資料之眼圖............................. 48
圖4-1(a) 整體電路之佈局平面圖............................. 51
圖4-1(b) 傳輸器佈局平面圖................................. 51
圖4-1(c) 接收器佈局平面圖................................. 51
圖4-2 下線佈局照相圖................................... 52
圖4-3 晶片使用之FR4印刷電路板(2.54cm)................. 52
圖4-4 實際晶片量測狀況圖............................... 53
圖4-5(a) 接收器還原之127位元亂數資料..................... 53
圖4-5(b) 量測兩位元亂數之頻率............................. 54
圖4-6(a) 接收器還原之127位元亂數資料..................... 54
圖4-6(b) 量測兩位元亂數之頻率............................. 54
圖4-7(a) 接收器還原之127位元亂數資料..................... 55
圖4-7(b) 量測兩位元亂數之頻率............................. 55
圖4-8(a) 接收器還原之127位元亂數資料..................... 56
圖4-8(b) 量測兩位元亂數之頻率............................. 56
圖4-9(a) 接收器還原訊號之眼圖(600MHz) .................... 57
圖4-9(b) 接收器還原訊號之眼圖(700MHz) .................... 57
圖4-9(c) 接收器還原訊號之眼圖(800MHz) .................... 58
圖4-10 晶片使用之FR4印刷電路板(10cm)................... 59
圖4-11(a) 接收器還原之127位元亂數資料(847MHz)............. 59
圖4-11(b) 接收器還原之127位元亂數資料(927MHz)............. 60
圖4-12(a) 接收器還原訊號之眼圖(750MHz).................... 60
圖4-12(b) 接收器還原訊號之眼圖(930MHz).................... 60
圖4-13(a) 接收器還原之127位元亂數資料..................... 61
圖4-13(b) 量測兩位元亂數之頻率............................. 61
圖4-13(c) 接收器還原訊號之眼圖............................. 62
圖4-14 輸入參考頻率為31.25MHz (1GHz)................... 62
圖4-15 量測鎖相迴路輸出訊號頻率(1GHz)................... 63
圖4-16(a) 量測鎖相迴路輸出訊號之Jitter...................... 63
圖4-16(b) 量測鎖相迴路除頻輸出訊號之Jitter.................. 63
附圖A1-1 鎖相迴路架構..................................... 72
附圖A1-2 鎖相迴路線性模組(Linear Model).................... 72
附圖A2-1 PFD方塊圖....................................... 73
附圖A2-2 PFD運作示意圖 (a)φR ≠ φV (b)ωR ≠ ωV.............. 74
附圖A2-3 傳統三態相位頻率偵測器[19]....................... 74
附圖A2-4 PFD電路圖[20]................................... 74
附圖A2-5 電荷幫浦架構圖[21]............................... 76
附圖A2-6 charge sharing問題分析............................. 76
附圖A2-7 charge pump電路圖[22]............................. 76
附圖A2-8 二階迴路濾波器................................... 77
附圖A2-9 四級環形振盪器電路結構圖[15]..................... 77
附圖A2-10 單位延遲電路圖[15]............................... 77
附圖A2-11 除2電路架構圖................................... 78
附圖A2-12 TSPC電路圖...................................... 78
附圖A2-13 除2電路時序圖................................... 78
附圖A2-14 除32電路架構圖.................................. 78
附圖A3-1 VCO之tuning range................................ 79
附圖A3-2 ref_clk相位領先vco_clk............................ 79
附圖A3-3 ref_clk相位落後vco_clk............................ 80
附圖A3-4 除頻器模擬圖..................................... 80
附圖A3-5 PLL尚未鎖定情形................................. 81
附圖A3-6 PLL鎖定情形..................................... 81
附圖A3-7 PLL鎖定下之VCO輸出波形........................ 82
附圖A3-8 PLL鎖定下 VCO之控制電壓變化圖................. 82
附圖A3-9 PLL在5種不同corner下鎖定情形.................... 83
附圖A3-10 PLL之jitter模擬圖................................. 83
附圖B-1 FR4印刷電路板剖面圖............................. 85
附圖B-2 FR4之spice檔.................................... 86
附圖B-3 傳輸線分析結果................................... 86
附圖B-4 傳輸線等效RLC模型.............................. 86
附圖C-1 封裝模型架構圖................................... 87

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