臺灣博碩士論文加值系統

多晶矽薄膜電晶體(poly-Si TFTs)基於其優於非晶矽薄膜電晶體(amorphous silicon TFTs)的電流驅動能力，最近在液晶顯示器(AMLCD)及有機發光二極體(AMOLED)顯示器的週邊電路整合應用上皆備受矚目。
論文的第二章對元件的可靠度以各種不同的偏壓條件及偏壓時間來衡量。我們將以本文所提出之枕木型佈局的電晶體作可靠度的量測以避免元件間初始特性差異過大，導致在同一偏壓條件下得到發散的結果。經由這些實驗資料將會對估計元件的生命週期和安全的操作區域將是十分有幫助的。另外，我們將針對低溫多晶矽薄膜電晶體(low temperature poly-Si TFTs)的元件C-V特性作的研究。對於在特定外加偏壓下的元件C-V特性，會做進一步的討論。以元件在自發熱效應(Self-Heating Effect)偏壓條件下的閘極/源極(CGS)與閘極/汲極(CGD)的電容電壓特性為例，可以發現，在這個操作條件前後，其CGS、CGD均呈現明顯的飄移，且CGS曲線在起始電壓附近呈現約40％的增加，而CGD曲線則僅呈現約10％的增加。經由模擬結果顯示，元件兩端的電容特性的差異主要來自於在自發熱效應操作條件下，其閘極/源極跨壓甚大，因此造成介面缺陷的增加，形成CGS後半段上升的行為。而閘極/汲極的跨壓較小，因此所受到的影響也較小。另一方面關於元件在熱載子效應下所受的電容電壓特性，可以發現其CGS曲線並未出現明顯的改變，然而CGD曲線則在起始電壓附近下降，並呈現明顯的頻率相依性。這些元件劣化行為的描述將可以用我們所提出的劣化模型加以描述，並以模擬軟體模擬其趨勢。最後，將劣化的電容模型代入環形震盪器裡並以H-SPISE模擬電容效應，發現電容對於電路的影響是甚為巨大的。

Low Temperature Polycrystalline Silicon (LTPS) thin film transistors (TFTs) have attracted much attention in the application on the integrated peripheral circuits of display electronics such as active matrix liquid crystal displays (AMLCDs) and active matrix organic light emitting diodes (AMOLEDs) due to its better current driving compared with a-Si (amorphous silicon) TFTs.
In the chapter two of this thesis, the reliability of LTPS TFTs is studied in form of stress map by adopting the crosstie layout TFTs to get the more consistent reliability behaviors. This database of reliability is very helpful to evaluate the lifetime and operation conditions of LTPS TFTs. In addition, we will focus on the C-V characteristic of the low temperature poly-Si TFTs and have further discussion of C-V characteristic under the specific bias voltage. As the example with the characteristic of voltage of C-V curve, it is found that before and after this condition of operating, its CGS & CGD presented obvious shift, and about 40% of the increase appears near the initial voltage in CGS curve, but only about 10% of the increase appears in CGD curve. The result shows the difference of characteristics of the C-V curve of both ends of the device comes from self-heating stress condition, the voltage difference between gate/source is very large, so cause the increase of the defect of interfaces, form one section of behaviors of rising of CGS latter half. And the voltage between gate and drain is smaller than that of gate and source, so the influence is slightly. Characteristic of C-V curve received under the hot carrier effect can find that its CGS curve has not presented the obvious change, but CGD curve drops near the initial voltage, and it is interdependent to present obvious frequency. The description of these component degradation behaviors can be described with the degradation model that we propose, and in order to imitate its trend of simulation. Finally , take the place of the model of C-V curve with the degradation one in ring oscillator and with H-SPISE simulation, find that the influence on the circuit of the electric capacity is very enormous.

Contents


Abstract (Chinese)…………………………………………………...Ⅰ
Abstract (English)……………………………………………………Ⅲ
Acknowledgements…………………………………………………..Ⅴ
Contents………………………………………………………………01



Chapter 1. Introduction
1-1. Introduction to LTPS TFTs…………………………………...03
1-2. Diverse reliability behaviors & Device variation…………….04
1-3. Defects in poly-Si TFTs…………………………………........05
1-4. Motivation…………………………………………………….06
1-5. Thesis outline………………………………………………….07
Chapter 2. The study of crosstie TFT device’s C-V characteristics
2-1. Initial C-V characteristics
2-1-1. Introduction to crosstie TFTs & device fabrication…….09
2-1-2. Parameter extraction method…………………………...10
2-2. Behavior of C-V curve after stressing
2-2-1. Stressing mapping of TFT
2-2-1-a. Grids of stress map……………………………........12
2-2-1-b. Degradation mechanism & discussion……………..13
2-2-3. N-type TFTs C-V characteristics degradation behavior...16
2-2-2. P-type TFTs C-V characteristics degradation behavior…20
2-3. Discussion…………………………………………………..24
Chapter 3. Effects of parasitic capacitance on circuit performance
3-1. Introduction to the ring oscillator………………………………25
3-2. Evaluation of the circuit performance with the consideration of proposed parasitic capacitance models…………………………………..27
3-3. Discussion and conclusion……………………………………...29
Chapter 4. Conclusion
References..................................................................................................32
Figure Captions…………………………………………………………...35
Figures and Tables

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