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研究生:蔡瑞夫
研究生(外文):Ruei-Fu Tsai
論文名稱:以管線方法改進非同步8051處理器之效能
論文名稱(外文):Using Pipeline Method to Improve Asynchronous 8051 Processor Performance
指導教授:陳昌居
指導教授(外文):Chang-Jiu Chen
學位類別:碩士
校院名稱:國立交通大學
系所名稱:資訊科學與工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2006
畢業學年度:94
語文別:英文
論文頁數:41
中文關鍵詞:8051非同步電路管線
外文關鍵詞:8051asynchronous circuitpipeline
相關次數:
  • 被引用被引用:1
  • 點閱點閱:288
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  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:2
8051是用途最廣的CISC處理器,因為指令長度不同,規則度也低,所以以往的實現方法都較少使用管線。管線設計的處理器,由於能夠平行處理,能夠提高整體產出。本論文之目的就是設計能在增加最少面積下,能提昇效能,以管線執行的8051處理器,稱為PA8051。
我們會將指令處理的步驟,分成Instruction Fetch (IF),Instruction Decode (ID),Operand Fetch (OF),Execution(EXE),Write Back (WB)這五個階段。管線執行的第一個重點是要能避免所有管線危障的情況,包括資料危障、結構危障、控制危障,本文中探討各種指令平行處裡可能發生的問題。第二重點在探討資料相依時,所要解決的方法。
最後的結果在行為模型下正確的通過了驗証,並以Xilinx合成器轉成電路。
8051 is the most popular CICS ISA Microprocessor, because of its different instruction length, the regulation of instruction is little. Its design is hard to implement in pipeline. The throughput of pipelined processor is higher than that of nonpipelined processor. The objective of this processor is to develop a pipelined asynchronous 8051 processor, called PA8051.
We divide PA8051 into five stages, that is Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Execution(EXE) and Write Back (WB). The most important problem to be resolved in pipelined design is hazard, including data hazard, structural hazard, control hazard. Thus, we analyze where the hazards happen and find the solution to solve the hazards.
Finally, we successfully passed the behavior simulation and synthesized the design with Xilinx Synthesize tool.
Contents iv
List of Figures v
List of Tables vi
Chapter 1. Introduction 1
1.1 Motivations 1
1.2 Asynchronous Design 1
1.3 Balsa Synthesis Tool 3
1-4 Organization of this thesis 5
Chapter 2. Related Work 6
2.1 Overview of 8051 6
2.2 Overview of Pipeline Architecture 8
2.3 Balsa back-End 9
2-3-1 Basic Elements 9
2-3-2 Handshake Components 11
2-4 Concluding Remarks 13
Chapter 3. Design of PA8051 14
3.1 The architecture of PA8051 14
3.2 The IF stage 16
3.3 The ID stage 16
3.4 The OF stage 17
3.5 The EXE stage 19
3.6 The WB stage 21
3.7 The Memory and Register Interface 23
3.8 The instruction execution stage 25
3.9 The Hazard control and data forwarding 25
3.9.1 Data Hazard 26
3.9.2 Control Hazard 30
Chapter 4. Implementation and Verification 31
4.1 The VLSI and FPGA design flow of asynchronous circuit using balsa 31
4.2 Implementation Issues 34
4.3 Verification 34
Chapter 5. Result 37
5.1 Simulation Result 37
5.2 Area Cost 37
Chapter 6. Conclusion and future work 39
References 40
[1] A. Bardsley, D. A. Edwards, “The Balsa Asynchronous Circuit Synthesis System” 2000. University of Manchester
[2]A. Bardsley, "Implementing Balsa Handshake Circuits," 2000. University of Manchester
[3] Doug Edwards, Andrew Bardsley, Lilian Janin & Will Toms“Balsa : A Tutorial Guide”, 2004.
[4] Hans van Gageldonk, Kees van Berkel_, Ad Peeters “An Asynchronous Low-Power 80C51 Microcontroller”, Philips Semiconductors, 2001.
[5] I.E. Sutherland, “Micropipelines”, Communications of the ACM, Vol.32, Number 6, June 1989, pp 720-738.
[6]I. KEIL Software, "8051 Development Tools," 2005.
[7] Je-Hoon Lee, et.al “A novel asynchronous pipeline architecture for CISC type embedded controller, A8051”, The 2002 45th Midwest Symposium on Circuits and Systems
[8] J.V.Wood et.al “AMULET1:An Asynchronous ARM Microprocessor”, IEEE Transactions on Computers, Volume 46, Issue 4, April 1997 Page(s):385 – 398
[9] Martin, A.J.,et.al”The Lutonium: a sub-nanojoule asynchronous 8051 microcontroller”, Asynchronous Circuits and Systems, 2003. Proceedings. Ninth International Symposium Page(s):14 – 23
[10]Q.Zhang & G.Theodoropoulos, “Modelling SAMIPS: A Synthesizable Asynchronous MIPS Processor”, Proceeding of the 37th Annul Simulation Symposium.
[11] S.B.Furber et.al“AMULET2e:An Asynchronous Embedded Controller”, Proceedings of the IEEE Volume 87, Issue 2, Feb. 1999 Page(s):243 - 256
[12] S.B.Furber et.al “AMULET3:A High-Performance Self-Timed ARM Microprocessor”, ICCD '98. Proceedings., Page(s):247 – 252
[13] Spars, J. Furber, S. “Principle of Asynchronous Circuit Design”, 2001. Kluwer Academic Publishers.
[14] Y.T.Chang, “SA8051:An asynchronous soft-core Processor for Low-Power System-on-Chip Applications”, 2005
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