臺灣博碩士論文加值系統

本論文之目標為實現一通用型資料回復器及解多工器電路，以期應用在高速串列傳輸收發機之內。此資料回復器電路係採用二倍超取樣技術，其主要內部電路包含多相位輸出之鎖相迴路、相位內插器、相位偵測器、計數器及暫存器。待還原之每筆輸入資料將經由二取樣相位進行取樣，其中取樣相位係由鎖相迴路之輸出相位內插而成，而相位內插之權值將預存於暫存器中。時脈回復過程中相位偵測器將比較取樣相位及輸入資料相位之相對誤差，藉此產生修正信號並回存於暫存器中，進而達到合成最佳資料取樣相位之目的。爲減少時脈回復過程所需耗費之時間，本論文提出結合二位元搜尋法及二倍速超取樣之資料回復電路架構，藉此大幅減少鎖定所需時間，同時利用多相位分時平行取樣技術，進而達到高速操作及低功率消耗之目的。此電路採用TSMC 0.18μm CMOS製程技術，操作電壓為1.8V之下，當資料頻率為3.125Gbps時，總功率消耗為78毫瓦。

目錄:

摘要…………………………………………………………………....i
致謝……………………………………………………………......iii
目錄…………………………………………………………………...iv
圖目錄………………………………………………………………...vi
表目錄……………………………………………………………….viii
第一章 簡介……………………………………………………………..1
1.1動機 ……………………………………………………………..1
1.2 時脈資料回復電路架構…………………………………………….2
1.3 論文組織 ………………………………………………………….3
第二章 時脈倍頻電路…………………………………………………4
2.1 簡介…………………………………………………………………4
2.2時脈倍頻電路架構……………………………………………………5
2.3時脈倍頻電路線性模型………………………………………………7
2.4電壓控制振盪器 ……………………………………………………9
2.5振盪器頻段控制電路……………………………………………..14
2.6除頻器與相位頻率偵測器 ………………………………………..17
2.7電荷幫浦電路……………………………………………………..21
2.8迴路濾波器設計…………………………………………………..22
2.9模擬與量測結果…………………………………………………..24
第三章 抖動分析……………………………………………………..29
3.1簡介………………………………………………………………..29
3.2抖動對錯誤率的影響 ……………………………………………..29
3.3抖動容忍度 ………………………………………………………..33
3.4模擬結果 …………………………………………………………..37
第四章 時脈資料回復電路…………………………………………..38
4.1簡介 ………………………………………………………………..38
4.1.1 CDR二種傳統架構 ………………………………………………38
4.1.2 CDR的架構,及其工作原理 …………………………………...40
4.2相位偵測器 ………………………………………………………..42
4.2.1 傳統Alexander式的架構 ……………………………………..42
4.2.2 改進後Alexander式相位偵測器 ………………………………44
4.3相位內插器 ………………………………………………………..46
4.4 數位-類比轉換器………………………………………………………….47
4.5 迴路濾波器………………………………………………………………..48
4.6 模擬以及量測結果………………………………………………………..52
第五章 結論……………………………………………………………59
參考文獻………………………………………………………………..61
簡歷……………………………………………………………………..63

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