臺灣博碩士論文加值系統

本論文提出一新穎之量測方法，並據以研究先進閘極介電層互補式金氧半電晶體中電壓溫度引致之不穩定性。此方法包括一自行組裝之電腦自動化量測電路系統，以及特殊設計之實驗技巧。傳統量測方法於加壓與量測之間，存在大約數秒之延遲，期間發生的電荷散逸將嚴重影響實驗數據的可信度與完整性。本論文所提之創新方法可有效縮短延遲至數微秒，成功攫取暫態訊號，發現新的現象並得以研究其物理。

第二章詳述此新穎量測電路之各零組件、系統效能、並展示於實際CMOS元件以及記憶體元件測試之量測結果。第三章介紹應用第二章所提之電路所發展之實驗方法—「暫態回復技巧」。此法之理論基礎與實際應用都將詳列於此章。吾人發現，經電壓溫度加壓，大面積元件具有可觀之回復效應；回復過程中，汲極電流對時間呈現log關係。同樣地，小面積元件亦有回復現象，但其汲極電流對時間的關係，則以不連續的、階梯式的圖像呈現。吾人研究發現，此量子化行為，乃一顆一顆儲存於介電層缺陷中的電荷散逸所致。藉由研究電場以及溫度對單電荷散逸之影響，吾人提出一可解析之物理模型—「熱助穿隧」，成功地解釋所得之實驗結果。此模型配合實驗結果，可進一步粹取缺陷特性，如活化能以及缺陷密度等等。最後，吾人以此方法比較不同閘極材料中缺陷的特性之異同。

第四章探討HfSiON nMOSFETs中正電壓溫度所引致之不穩定性（PBTI）。有別於傳統量測，本研究以第二章所述之量測方法發現，延遲轉換將嚴重低估PBTI所造成的退化量。吾人實驗結果發現PBTI引致之汲極電流退化呈現兩階段（two-stage degradation）發展。第一個階段由填補初始缺陷（initial trap filling）主導退化，具log時間關係並與溫度呈現負相關。第二階段，額外缺陷產生（additional trap generation）的效應將超越初始缺陷填補，成為退化主因；此階段與時間成指數（power-law）關係並與溫度成正相關。此外，吾人利用第二章所提之單電荷散逸量測和暫態回復技巧、輔以常用的電荷幫浦（charge pumping）法所得之實驗結果，與前述退化模型相呼應。最後評估的是製程對缺陷產生以及兩階段退化特性的影響。

第五章研究HfSiON pMOSFETs中負電壓溫度所引致之不穩定性（NBTI）。低電壓或者室溫加壓，汲極電流退化的現象與一般預期無異：隨加壓時間呈現一路退化的趨勢、增加電壓強度或溫度則退化更嚴重。但再升高電壓或溫度，吾人則觀察到汲極電流隨時間之變化呈現奇特的「轉彎現象」（turn-around）：一開始汲極電流增加，到某時間點增加至最大值後開始降低，其後便一路減少並回歸到電流退化。愈高電壓以及愈高溫度下愈明顯。在本研究所有實驗條件下，在10秒以前汲極電流都會進入退化，所以一般量測方法若是忽略暫態效應，將無法清楚地觀測到此特殊現象。吾人提出一「雙極電荷模型」成功解釋實驗結果，並再次以單電荷散逸量測、以及電荷幫浦法，驗證所提出之物理模型。

最後於第六章，吾人總結本論文之貢獻，並提出未來研究方向的建議。

This thesis proposes a novel characterization methodology to study the bias temperature instability (BTI) in advanced gate dielectrics (mainly high-k) for CMOS technology. The methodology includes a computer-automated measurement circuit system and specially-designed experimental techniques. The system minimizes the switching delay between stress and measurement down to ~�酨, and successfully retrieves the valuable information which has been ignored in a conventional method where during the switching delay significant charge de-trapping takes place.

The components, capabilities, and demonstrations of the proposed transient measurement system are described in detail in Chapter 2. In Chapter 3, a novel recovery transient technique involving direct measurement of single charge phenomena is presented. Both large- and small-area MOSFETs are characterized. In a large-area device, the post-BTI drain current exhibits a recovery transient and follows logarithmic time dependence. In a small-area device, individual trapped charge emission from gate dielectric traps is observed during recovery, which is manifested by a staircase-like drain current evolution with time. By measuring the effects of electric field and temperature on the charge emission times, one can identify the physical mechanism for charge escape. An analytical model based on thermally assisted tunneling can successfully reproduce measured transient characteristics. One can also extract trap properties such as the activation energy and the trap density. Applications of the technique to comparison between different gate dielectric materials are also demonstrated.
Drain current degradation in HfSiON gate dielectric nMOSFETs due to positive bias and temperature (PBT) stress is investigated in Chapter 4 by using the fast transient measurement system introduced in Chapter 2. The degradation exhibits two stages, featuring different degradation rates and stress temperature dependence. The first stage degradation is attributed to charging of the pre-existing high-k dielectric traps and has log(t) dependence on stress time and negative temperature dependence while the second stage degradation is mainly caused by new high-k trap creation following a power-law time relation and positive temperature dependence. The high-k trap growth rate is characterized by two techniques, the recovery transient technique proposed in Chapter 3 and the well-known charge pumping technique. Finally, the impact of processing on high-k trap growth is evaluated.

In Chapter 5, negative bias temperature instability (NBTI) is explored for pMOSFET’s with HfSiON as the high-k gate dielectric. An anomalous turn-around in NBT stress induced drain current change is observed. For low stress gate voltage amplitude (|Vg|) and/or low temperature, the drain current degrades with time and increase in stress strength aggravates the degradation. Further increase in (|Vg|) and/or in temperature, in contrast, leads to an anomalous turn-around in the temporal evolution of drain current. The drain current initially enhances, reaches a peak, goes downhill, and eventually enters degradation. The phenomenon occurs within 10 seconds for most stress conditions in this work, and thus is easily neglected in a conventional method. The measured enhancement grows with increasing stress |Vg| and temperature. A physical model incorporating bipolar charge trapping is proposed to account for the experimental results. Direct measurement of single charge de-trapping and charge pumping measurement are performed and the results justify the model.

Finally, the contributions of this dissertation are summarized and the directions for the future works are suggested in Chapter 6.

Chinese Abstract i
English Abstract iii
Acknowledgement v
Contents vii
Table Captions ix
Figure Captions x
List of Symbols xvi

Chapter 1 Introduction 1
1.1 Backgrounds 1
1.2 Description of the Problem 3
1.3 Organization of the Dissertation 4

Chapter 2 A Fast -Transient Measurement System and Experimental Techniques 9
2.1 Necessity of Transient Measurement 9
2.2 Existing Techniques 10
2.2.1 RF Kits 10
2.2.2 Series Resistance 11
2.2.3 Operational Amplifiers 12
2.3 A Computer-Automated Measurement System 12
2.3.1 The System 12
2.3.2 System Capability 13
2.4 Summary 14

Chapter 3 Single Charge Emission: A Novel Technique to Investigate Trap Properties in Advanced Gate Dielectrics 25
3.1 Preface 25
3.2 Recovery Transient Measurement 26
3.2.1 Experimental 26
3.2.2 Recovery Transient in Large-Area Devices 27
3.2.3 Single Electron Emission in Small-Area Devices 28
3.3 Results and Discussions 29
3.3.1 The Trapped Charge Emission Model 29
3.3.2 High-k Trap Density 31
3.3.3 Modeling of Recovery Transient in Large-Area Devices 32
3.3.4 Gate Length Effect 36
3.4 Applications of the Technique 36
3.4.1 Study of NBTI in SiO2 pMOSFETs 36
3.4.2 Comparison between High-k and SiO2 37
3.5 Summary 38

Chapter 4 Characteristics and Physical Mechanisms of Positive Bias and Temperature Stress Induced Drain Current Degradation in HfSiON nMOSFETs 57

4.1 Preface 57
4.2 Devices 58
4.3 Two-Phase Measurement 58
4.4 Results and Discussions 59
4.4.1 Two-Stage Drain Current Degradation 59
4.4.2 The Degradation Model 60
4.4.3 High-k Trap Growth Rate 61
4.4.4 The Impact of Processing 65
4.5 Summary 66

Chapter 5
Negative Bias Temperature Instability in High-k pMOSFETs 88
5.1 Preface 88
5.2 Devices 89
5.3 Anomalous Turn-Around in Drain Current Degradation 89
5.4 The Bipolar Charging Model 90
5.5 Charge Pumping and Single Charge Emission 92
5.6 Impact of High-k Integrity 93
5.7 Summary 94

Chapter 6 Conclusions 109
6.1 Summary of Contributions 109
6.2 Suggestions for Future Works 110

References 111
Vita 125
Publication List 126

References
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Chapter 2
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Chapter 3
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[3.2] C. T. Chan, C. J. Tang, C. H. Kuo, H. C. Ma, C. W. Tsai, H. C. H. Wang, M. H. Chin, and Tahui Wang, “Single-electron emission of eraps in HfSiON as high-k gate dielectric for MOSFETs,” Proc. Int. Reliab. Phys. Symp., pp. 41-44, 2005
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[3.6] R. Degraeve, A. Kerber, P. Roussell, E. Cartier, T. Kauerauf, L. Pantisano, G. Groeseneken, “Effect of bulk trap density on HfO2 reliability and yield,” IEDM Tech. Dig., pp. 935-938, 2003
[3.7] R. Degraeve, F. Crupi, D. H. Kwak, and G. Groeseneken, “On the defect generation and low voltage extrapolation of QBD in SiO2/HfO2 stacks,” VLSI Tech. Dig. pp. 140-141, 2004
[3.8] H.C.-H. Wang, S.-J. Chen, M.-F. Wang, P.-Y. Tsai, C.-W. Tsai, T.-W. Wang, S.M. Ting, T.-H. Hou, P.-S. Lim, H.-J. Lin, Y. Jin, H.-J. Tao, S.-C. Chen, C.H. Diaz, M.-S. Liang, and C. Hu, “Low power device technology with SiGe channel, HfSiON, and poly-Si gate,” IEDM Tech. Dig., pp. 161-164, 2004
[3.9] H.C.-H. Wang, C. W. Tsai, S. J. Chen, C. T. Chan, H. J. Lin, Y. Jin, H. J. Tao, S. C. Chen, C. H. Diaz, T. Ong, A. S. Oates, M. S. Liang, and M. H. Chi, “Reliability of HfSiON as gate dielectric for advanced CMOS technology,” accepted, VLSI Tech. Dig., pp. 170-171, 2005
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[3.16] M. A. Alam, “NBTI: Modeling,” IRPS short course, 2005
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Chapter 4
[4.1] N. Kimizuka, T. Yamamoto, T. Mogami, K. Yamaguchi, K. Imai, and T. Horiuchi, “The impact of bias temperature instability for direct-tunneling ultra-thin gate oxide on MOSFET scaling,” VLSI Tech. Dig. pp. 73-74, 1999
[4.2] H. C.-H. Wang, C. W. Tsai, S. J. Chen, C. T. Chan, H. J. Lin, Y. Jin, H. J. Tao, S. C. Chen, C. H. Diaz, T. Ong, A. S. Oates, M. S. Liang, and M. H. Chi, “Reliability of HfSiON as gate dielectric for advanced CMOS technology,” VLSI Tech. Dig. pp. 170-171, 2005
[4.3] S. Zafar, A. Callegari, E. Gusev, and M. V. Fischetti, “Charge trapping in high K gate dielectric stacks,” IEDM Tech. Dig., pp. 517-520, 2002
[4.4] S. Zafar, A. Callegari, E. Gusev, and M. V. Fischetti, “Charge trapping related threshold voltage instabilities in high permittivity gate dielectric stacks,” J. Appl. Phys., vol. 93, pp. 9298-9303, 2003
[4.5] A. Shanware, M. R. Visokay, J. J. Chambers, A. L. P. Rotondaro, H. Bu, M. J. Bevan, R. Khamankar, S. Aur, P. E. Nicollian, J. McPherson, and L. Colombo, “Evaluation of the positive bias temperature stress stability in HfSiON gate dielectrics,” Proc. Int. Reliab. Phys. Symp., pp. 208-213, 2003
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[4.7] C. T. Chan, C. J. Tang, T. Wang, H. C.-H. Wang, and D. D. Tang, “Positive bias and temperature stress induced two-stage drain current degradation in HfSiON nMOSFET’s,” IEDM Tech. Dig., pp. 571-574, 2005
[4.8] C. T. Chan, H. C. Ma, C. J. Tang, and T. Wang, “Investigation of post-NBTI stress recovery in pMOSFETs by direct measurement of single oxide charge de-trapping,” VLSI Tech. Dig. pp. 90-91, 2005
[4.9] T. Wang, C. T. Chan, C. J. Tang, C. W. Tsai, H. C.-H. Wang, M. H. Chi, and D. D. Tang, “A novel transient characterization technique to investigate trap properties in HfSiON Gate Dielectric MOSFETs – from single electron emission to PBTI recovery transient,” to appear in IEEE Trans. on Elec. Dev., 2006
[4.10] H. C.-H. Wang, S.-J. Chen, M.-F. Wang, P.-Y. Tsai, C.-W. Tsai, T.-W. Wang, S.M. Ting, T.-H. Hou, P.-S. Lim, H.-J. Lin, Y. Jin, H.-J. Tao, S.-C. Chen, C.H. Diaz, M.-S. Liang, and C. Hu, “Low power device technology with SiGe channel, HfSiON, and poly-Si gate,” IEDM Tech. Dig., pp. 161-164, 2004
[4.11] T. Yang, M. F. Li, C. Shen, C. H. Ang, C. Zhu, Y. C. Yeo, G. Sam udra, S. C. Rustagi, M. B. Yu, and D. L. Kwong, “Fast and slow dynamic NBTI components in p-MOSFET with SiON dielectric and thrie impact on device life-time and circuit application,” VLSI Tech. Dig. pp. 92-93, 2005
[4.12] R. Degraeve, A. Kerber, P. Roussell, E. Cartier, T. Kauerauf, L. Pantisano, G. Groeseneken, “Effect of bulk trap density on HfO2 reliability and yield,” IEDM Tech. Dig., pp. 935-938, 2003
[4.13] R. Degraeve, F. Crupi, D. H. Kwak, and G. Groeseneken, “On the defect generation and low voltage extrapolation of QBD in SiO2/HfO2 stacks,” VLSI Tech. Dig. pp. 140-141, 2004
[4.14] T. Yamaguchi, I. Hirano, R. Iijima, K. Sekine, M. Takayanagi, K. Eguchi, Y. Mitani, and N. Fukushima, “Thermochemical understanding of dielectric breakdown in HfSiON with current acceleration,” Proc. Int. Reliab. Phys. Symp., pp. 67-74, 2005
[4.15] I. Lundstrom and C. Svensson, “Tunneling to traps in insulators,” J. of Appl. Phys., vol. 43, pp. 4045-5047, 1972
[4.16] D. A. Adams, J. T. Smith, J. R. Murray, A. H. White, and S. Wrazien, ”Design, fabrication ,and characterization of high-density radiation hardened SONOS/CMOS EEPROMs for space and military systems,” Proc. Non-Volatile Memory Tech. Symp., pp. 60-65, 2004

Chapter 5
[5.1] S. Zafar, B. H. Lee, J. Stathis, A. Callegari, and T. Ning, ”A model for negative bias temperature instability (NBTI) in oxide and high-k pFETs,” VLSI Tech. Dig. pp. 208-209, 2004
[5.2] M. Houssa, S. De Gendt, J. L. Autran, G. Groeseneken, and M. M. Heyns, ”Detrimental impact of hydrogen on negative bias temperature instabilities in HfO2-based pMOSFETs,” VLSI Tech. Dig. pp. 212-213, 2004
[5.3] M. Houssa, M. Aoulaiche, S. Van Elshocht, S. De Gendt, G. Groeseneken, and M. M. Heyns, ”Impact of Hf content on negative bias temperature instabilities in HfSiON-based gate stacks,” Appl. Phys. Lett., vol. 86, pp. 173509, 2005
[5.4] T. Wang, C. T. Chan, C. J. Tang, C. W. Tsai, H. C.-H. Wang, M. H. Chi, and D. D. Tang, “A novel transient characterization technique to investigate trap properties in HfSiON Gate Dielectric MOSFETs – from single electron emission to PBTI recovery transient,” to appear in IEEE Trans. on Elec. Dev., 2006
[5.5] S, Rangan, N. Mielke, and E. C. C. Yeh, “Universal recovery behavior of negative bias temperature instability,” IEDM Tech. Dig., pp. 341-344, 2003
[5.6] T. Yang, M. F. Li, C. Shen, C. H. Ang, C. Zhu, Y. C. Yeo, G. Sam udra, S. C. Rustagi, M. B. Yu, and D. L. Kwong, “Fast and slow dynamic NBTI components in p-MOSFET with SiON dielectric and thrie impact on device life-time and circuit application,” VLSI Tech. Dig. pp. 92-93, 2005
[5.7] H. C.-H. Wang, C. W. Tsai, S. J. Chen, C. T. Chan, H. J. Lin, Y. Jin, H. J. Tao, S. C. Chen, C. H. Diaz, T. Ong, A. S. Oates, M. S. Liang, and M. H. Chi, “Reliability of HfSiON as gate dielectric for advanced CMOS technology,” VLSI Tech. Dig. pp. 170-171, 2005
[5.8] H. C.-H. Wang, S.-J. Chen, M.-F. Wang, P.-Y. Tsai, C.-W. Tsai, T.-W. Wang, S.M. Ting, T.-H. Hou, P.-S. Lim, H.-J. Lin, Y. Jin, H.-J. Tao, S.-C. Chen, C.H. Diaz, M.-S. Liang, and C. Hu, “Low power device technology with SiGe channel, HfSiON, and poly-Si gate,” IEDM Tech. Dig., pp. 161-164, 2004
[5.9] C. T. Chan, C. J. Tang, T. Wang, H. C.-H. Wang, and D. D. Tang, “Positive bias and temperature stress induced two-stage drain current degradation in HfSiON nMOSFET’s,” IEDM Tech. Dig., pp. 571-574, 2005
[5.10] C. T. Chan, H. C. Ma, C. J. Tang, and T. Wang, “Investigation of post-NBTI stress recovery in pMOSFETs by direct measurement of single oxide charge de-trapping,” VLSI Tech. Dig. pp. 90-91, 2005

Chapter 6
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