臺灣博碩士論文加值系統

本論文研製一個應用於超寬頻3.1-10.6 GHZ的低雜訊放大器是採用電阻-電感回授做輸入匹配，而在輸出端是用current buffer做匹配。本研究是以0.18微米互補式金氧半製程實現。此低雜訊放大器是以三級放大為主架構，第一級為RL-feedback結構，是為了增加頻寬，第二級為傳統的CS結構，可以增加平均順向增益(S21)，第三級則是current buffer，主要是在輸出端做匹配。為了能在所應用的頻段內達到相對的平坦增益，在前兩級中利用shunt peaking 的方法去實現。供應電壓VDD為1.8伏特時，整個電路功率消耗約為23.04mW，及包含pad的情況下整個電路大小約為0.776 mm2。本研究的低雜訊放大器所量測的規格，平均順向增益(S21)在3.1-10.6GHz時為6.9dB-4.5dB，逆向隔離(S12)為-33dB以下，S11為-10dB以下，S22約為-16dB以下，而平均雜訊指數約為6dB。

A 3.1-10.6 GHZ low noise amplifier is applied for ultra-wideband, it introduces RL feedback for input matching. And current buffer is used for output matching. This research is fabricated in 0.18-μm CMOS process. Three amplified stages are formed for main topology in low noise amplifier. The first stage introduces RL-feedback configuration, it can improve the bandwidth. The second stage introduces traditional CS configuration, it can improve the average forward S21. The third stage introduces current buffer configuration, it is used for output matching. Relatively flat gain is essential over the entire desired band. The low noise amplifier introduces the shunt peaking to achieve the above purpose. The total power dissipation of the chip is about 29 mW at power supply 1.8 volt. The chip size included pad is 0.776 mm2. The measurement result of this study expect that the average forward S21 is 6.9dB at 3.1-10.6GHz, the reverse isolation S12 is under -33dB, the magnitude of S11 is under -10 dB, the magnitude of S22 is under -16dB, and the noise figure is 6dB.

Abstract (in Chinese) I
Abstract (in English) II
誌謝 III
Contents IV
Figure Captions VI
Chapter 1 Introduction
1.1 UWB CMOS Receivers 1
1.2 Motivation 2
Chapter 2 Issues in RFIC Design
2.1 Noise Analysis
2.1.1 The Concept of Noise Figure 4
2.1.2 The Noise Figure of an Amplifier Circuit 6
2.2 Linearity in RF Circuit 9
2.2.1 Third-Order Intercept point and The 1-dBCompression Point 11
2.2.2 Cascaded Nonlinear Stages 14
Chapter 3 Basic LNA Design
3.1 Consideration in Low-Noise Amplifiers
3.1.1 Impedance Matching 18
3.1.2 Stability 25
3.2 Wide-band LNA design 27
Chapter 4 UWB CMOS LNA Design
4.1 Design Procedures 32
4.1.1 Inductor-Resistance Feedback 35
4.1.2 Shunt Peaking 39
4.2 Simulation Results 41
4.3 Measurements and Conclusions 45
Chapter 5 Summary 50
References 51
Vita 55

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