臺灣博碩士論文加值系統

本論文的研究方向，主要為研發新穎之雙功函數金屬閘極製程技術。元件尺寸的微縮雖可以改善元件之操作特性，然而傳統的多晶矽閘極本質上的缺點，對元件特性的負面影響也將更加顯著。另一方面，隨著元件尺寸的微縮，閘極氧化層的厚度變薄也將導致閘極漏電流大幅上揚，為了有效降低閘極漏電流，近年來以高介電材質取代傳統二氧化矽的相關研究也被投注大量心力。然而多晶矽閘極搭配高介電材質，已被發現會有熱穩定性不佳的缺點，同時介面也存在著費米能階夾止效應，因此，金屬閘極製程的研發不僅可以克服上述多晶矽的本質缺點，對於與高介電材質間的熱穩定性、費米能階夾止效應等方面，也提供了可能的解答。此外，金屬閘極的低阻抗，對於元件的高頻操作特性亦有改善之效。
對於金屬閘極的製程技術與材料選擇有以下幾項基本要求，首先它必須能夠在閘極介電層介面提供正確適當的功函數值，同時與閘極介電層間需有良好的熱穩定性以確保在元件製程中可以保有穩定的特性，另外也必須可相容、整合於傳統的製程技術中。本論文中，我們提出了兩種新穎的雙功函數金屬閘極製程技術，一是利用金屬混合以形成雙元合金，二是以金屬矽化反應以形成金屬矽化物。應用了此等金屬功函數調變法後，早期被提出的雙功函數金屬閘極製程技術中，閘極介電層因金屬蝕刻導致厚度的不均勻性以及可靠度退化的現象將可被避免。在雙元合金的實驗中，我們先以同時性濺鍍的物理沈積法沈積鉿鉬雙元合金，藉以觀察其電性、化性。藉由改變各靶材的濺鍍功率可調變鉿鉬合金的組成，進而得到近乎線性且連續的功函數調變，其調變範圍可介於3.93eV（純金屬鉿）與4.93eV（純金屬鉬）之間。我們也發現鉿鉬合金在二氧化矽上的熱穩定性，雖然會隨著鉿含量的增加而變差，但至少都可達400℃以上。
基於製程整合上的考量，我們進一步驗證了沈積鉿、鉬兩金屬層並經熱處理使其混合的方式以形成鉿鉬雙元合金，並藉此提出一雙功函數金屬閘極製程技術。由於達到完全的金屬混合以形成雙元合金所需的熱預算取決於兩金屬層的厚度總和TM (TM = THf + TMo)，我們提出了一個概念：根據金屬沈積後製程所需經過的總熱處理預算，選用適當的金屬層總厚度，則可以避免掉對金屬閘極材質本身熱穩定性的要求。此外，我們也驗證了藉由改變鉿、鉬兩金屬層的厚度比例TR (TR = THf / TMo)，可以精確地控制所形成的雙元合金的組成以及功函數值。上述的技術對於具有先進結構的元件諸如：FinFET、UTB-MOSFET將相當具有吸引力，因為先進元件通常具有較薄的基板厚度，且基板的雜質摻雜濃度對元件臨界電壓的調變效果也大幅降低。此外，先進元件所需的閘極功函數值會隨基板厚度與閘極數目的不同而有所差異，因此準確的功函數調變將會益形重要。
論文中所提出的第二種雙功函數金屬閘極製程技術則是應用了金屬的矽化反應。我們選擇在具有良好熱穩定性的金屬鉬上沈積了適當厚度的非晶矽，再藉由熱處理過程使其經由矽化反應生成矽化鉬，並藉此提出使用金屬鉬與矽化鉬作為閘極組合的雙功函數金屬閘極製程技術。在二氧化矽上，金屬鉬-矽化鉬之閘極組合所提供的功函數組合可適用於具有先進結構的元件，且矽化鉬亦被驗證具有良好的熱穩定性。另外我們發現在矽化反應之前，如果於非晶矽中佈植摻雜入雜質砷，則可進一步降低所生成矽化鉬的功函數值，進而拉大金屬鉬-矽化鉬之間的功函數差，將所提出的雙功函數金屬閘極製程技術之應用範圍擴大到傳統的本體元件。值得一提的是，此提出的新穎製程技術是利用金屬本身搭配本質或n型金屬矽化物來提供功函數差，有別於近期被廣泛研究的FUSI技術中利用p型與n型金屬矽化物來提供功函數差。由於避免了p型金屬矽化物的使用，因此可以消除硼穿透可能帶來的缺點。
我們同時也驗證了金屬鉬-矽化鉬之閘極組合在高介電材質上的特性。我們發現金屬鉬與矽化鉬在二氧化鉿的高介電閘極介電層上所得到的功函數值都分別略低於在二氧化矽上所得到的值，然而兩者間的功函數差值卻可維持。同時，矽化反應之前，於非晶矽中雜質砷的佈植仍然可以有效降低所形成矽化鉬在二氧化鉿上的功函數值，克服了FUSI技術在二氧化鉿高介電閘極介電層上，p型與n型金屬矽化物幾乎無功函數差的致命缺點。相較於FUSI技術，雖然同樣運用到金屬的矽化反應，然而我們的實驗結果卻顯示出費米能階夾止效應被有效壓抑。對此我們猜測其原因是：我們所提出的金屬鉬-矽化鉬雙功函數金屬閘極製程技術，其結構有效避免了非晶矽層在沈積過程以及矽化反應之前與高介電閘極介電層的直接接觸。

Two novel dual work function metal gate technologies are investigated and proposed. With the down-scaling of the device geometry for performance improvement, inherent drawbacks of conventional polysilicon gate electrodes lead to increasingly significant negative influence. In addition, the high-k gate dielectrics have been introduced to replace the conventional silicon dioxide. Consequently, under the same effective oxide thickness, the gate leakage current can be effectively reduced. Unfortunately, polysilicon gates have been reported to be thermodynamically unstable on many high-k materials and lead to Fermi-level pinning effect at the polysilicon/high-k interface. Therefore, metal gates are expected to provide a turning point in possessing a better thermal stability and a retardation of the Fermi-level pinning effect. In addition, metal gates can possess a lower gate resistance and enhance the device performance at higher frequency.
The basic requirements for a novel metal gate technology include providing suitable work function values at the gate dielectric interface, the good enough thermal stability with the underlying gate dielectrics and a compatible device integration process. Two novel metal gate technologies are proposed in this dissertation. One is based on the metal intermixing technique, and the other is based on the silicidation technique. We firstly investigate the electrical and chemical characteristics of Hf-Mo binary alloys deposited by co-sputtering technique. A continuous and almost linear work function adjustment using HfxMo(1-x) is demonstrated for the first time. The work function value of Hf-Mo binary alloy ranges from 3.93eV (work function of pure Hf) to 4.93eV (work function of pure Mo) and depends on the sputtering power ratio of each target. The thermal stabilities of Hf-Mo binary alloy on SiO2 are found to degrade with the increase of Hf atomic fraction, but all of the Hf-Mo binary alloys possess thermal stabilities at least higher than 400℃. The Hf-Mo binary alloys can be appropriate for a gate-last SiO2 CMOS process.
The practicable integration of Hf-Mo binary alloys into the dual metal gate process is also proposed. HfxMo(1-x) formed by metal intermixing of the Hf/Mo stack is firstly evaluated, and a novel dual work function metal gate technology is then proposed and demonstrated. A precise control over the work function of the Hf-Mo binary alloy by adjusting the composite metal thickness ratio TR (TR = THf / TMo) is demonstrated. Besides, the required thermal budget for a complete metal intermixing is demonstrated to depend on the total metal thickness, TM (TM = THf + TMo). Therefore, one can be allowed to get around the thermal stability issue by using an appropriate TM value. This technique is not only attractive but especially important for devices with advanced transistor structures, such as FinFET and/or UTB-MOSFET devices, since the substrate doping modulation may not be an efficient way to adjust the threshold voltages of devices with advanced transistor structures.
The other novel dual metal gate technology proposed in this dissertation is based on using the silicidation technique. The amorphous-Si/Mo stack was fabricated and thermal annealed to form MoSix. The work function of MoSix is found to be lower than that of Mo, and the thermal stability of MoSix is evaluated to be higher than 950℃. Combining MoSix with the pure Mo gate, a practical integration into the dual metal gate technology is then proposed. On the SiO2 gate dielectric, the combination of Mo-MoSix possesses a work function shift appropriate for devices with advanced transistor structures. Furthermore, the additional arsenic pre-implantation into the amorphous-Si layer prior to the silicidation annealing is demonstrated to effectively lower the work function of MoSix. Consequently, the application of the proposed novel dual metal gate technology can be expanded to the conventional bulk devices. Besides, the new structure along with the ruling out of p-type metal silicide is also demonstrated to eliminate the boron penetration problem encountered with the reported FUSI method.
On high-k gate dielectric materials, the maintenance of the considerable work function shift is also demonstrated. The extracted work function value of pure Mo or MoSi2 gate on HfO2 is slightly lower than that on SiO2, but the work function difference between Mo and MoSix is almost the same regardless of the underlying gate dielectric materials. The arsenic pre-implantation still has effect upon the modulation of work function of metal silicide on HfO2, even though the modulation range is a little smaller than that on SiO2. The influence of Fermi-level pinning effect, which has been reported to be responsible for the high threshold voltages of FUSI gated devices with the high-k gate dielectric, is also discussed. The Fermi-level pinning effect seems to be retarded in the proposed Mo-MoSix dual metal gate technology. We speculate that the improvement may be attributed to the separation of silicon layer from the high-k gate dielectrics.

Contents
Abstract (Chinese) i
Abstract (English) v
Acknowledgement viii
Contents x
Table Captions xiii
Figure Captions xiv

Chapter 1 Introduction
1.1 Evolution of Gate Electrode Candidates 1
1.2 Basic Requirements for Metal Gates 4
1.3 Metal Work Function Extraction Technique 6
1.4 Organization of the Thesis 8
References 11

Chapter 2 Investigation of HfxMo(1-x) Binary Alloys
2.1 Backgrounds and Motivation 23
2.2 Experiment 25
2.3 Results and Discussion 26
2.4 Summary 29
References 30

Chapter 3 Integratable Dual Metal Gate Technology Using
HfxMo(1-x) Binary Alloys
3.1 Backgrounds and Motivation 46
3.2 Experiment 47
3.3 Results and Discussion 48
3.4 Summary 51
References 52

Chapter 4 Novel Dual Metal Gate Technology Using MoSix
Films
4.1 Backgrounds and Motivation 62
4.2 Experiment 64
4.3 Results and Discussion 66
4.4 Summary 70
References 72

Chapter 5 Investigation of MoSix Based Dual Metal Gate
Technology on the High-k Gate Dielectric
5.1 Backgrounds and Motivation 96
5.2 Experiment 99
5.3 Results and Discussion 99
5.4 Summary 101
References 102

Chapter 6 Conclusions and Suggestions for Future Work
6.1 Contributions of the Study 111
6.2 Suggestions for Future Work 113

Vita (Chinese)
Publication List

Chapter 1
[1] M-L Chen, W. T. Cochran, T. S. Yang, C. Dziuba, C-W. Leung, W. Lin, and W. Jungling, “Constraints in p-channel device engineering for submicron CMOS technologies,” in IEDM Tech. Dig., 1988, pp. 390-393.
[2] F. K. Baker, J. R. Pfiester, T. C. Mele, H.-H. Tseng, P. J. Tobin, J. D. Hayden, C. D. Gunderson, and L. C. Parrillo, “The influence of fluorine on threshold voltage instabilities in p+ polysilicon gated p-channel MOSFETs ,” in IEDM Tech. Dig., 1989, pp. 443-446.
[3] J. M. Sung, C. Y. Lu, M. L. Chen, S. J. Hillenius, W. S. Lindenberger, L. Manchanda, T. E. Smith, and S. J. Wang,, “Fluorine effect on boron diffusion of p+ gate devices,” in IEDM Tech. Dig., 1989, pp. 447-480.
[4] K. F. Schuegraf, C. C. King, and C. Hu, “Impact of polysilicon depletion in thin oxide MOS technology,” in Proc. Tech. Papers 1993 Int. Symp. VLSI Technology, Systems, and Applications, 1993, pp.86-90.
[5] H. F. Luan, B. Z. Wu, L. G. Kang, R. Vrtis, D. Roberts, and D. L. Kwong, “Ultra thin high quality Ta2O5 gate dielectric prepared by in-situ rapid thermal processing,” in IEDM Tech. Dig., 1998, pp.609-612.
[6] C. H. Lee, H. F. Luan, W. P. Bai, S. J. Lee, T. S. Jeon, Y. Senzaki, D. Roberts, and D. L. Kwong, “MOS characteristics of ultra thin rapid thermal CVD ZrO2 and Zr silicate gate dielectrics,” in IEDM Tech. Dig., 2000, pp.27-30.
[7] B. Cheng, M. Cao, R. Rao, A. Inani, P. V. Voorde, W. M. Greene, J. M. C. Stork, Z. Yu, P. M. Zeitzoff, and J. C. S. Woo, “The impact of high-k gate dielectrics and metal gate electrodes on sub-100 nm MOSFETs,” IEEE Trans. on Electron Devices, vol. 46, pp.1537-1544, July 1999.
[8] E. Josse and T. Skotnicki, “Polysilicon gate with depletion or metallic gate with buried channel: What evil worse,” in IEDM Tech. Dig., 1999, pp.661-664.
[9] Qiang Lu, Y. C. Yeo, Pushkar Ranade, Hideki Takeuchi, T. J. King, and C. Hu, “Dual-metal gate technology for deep-submicron CMOS transistors,” in Symp. on VLSI Tech., 2000, pp.72-73.
[10] Y. C. Yeo, Qiang Lu, Pushkar Ranade, Hideki Takeuchi, K. J. Yang, I. Polishchuk, T. J. King, C. Hu, S. C. Song, H. F. Luan, and D.-L. Kwong, “Dual-metal gate CMOS technology with ultrathin silicon nitride gate dielectric,” IEEE Electron Device Letters, vol.22, no.5, pp.227-229, May 2001.
[11] Z. B. Zhang, S. C. Song, C. Huffman, J. Barnett, N. Moumen, H. Alshareef, P. Majhi, M. Hussain, M. S. Akbar, J. H. Sim, S. H. Bae, B. Sassman, and B. H. Lee, “Integration of dual metal gate CMOS with TaSiN (NMOS) and Ru (PMOS) gate electrodes on HfO2 gate dielectric, ” in Symp. on VLSI Tech., 2005, pp.50-51.
[12] D. Hisamoto, W.-C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, E. Anderson, T.-J. King, J. Bokor, and C. Hu, “FinFET – A self-aligned double-gate MOSFET scalable to 20nm,” IEEE Trans. on Electron Devices, vol. 47, pp.2320-2325, Dec. 2000.
[13] Leland Chang, Stephen Tang, T. J. King, Jeffrey Bokor, and C. Hu, “Gate length scaling and threshold voltage control of double-gate MOSFETs,” in IEDM Tech. Dig., 2000, pp. 719-722.
[14] X. Huang, W.-C. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski, E. Anderson, H. Takeuchi, Y.-K. Choi, K. Asano, V. Subramanian, T.-J. King, J. Bokor, and C. Hu, “Sub-50 nm p-channel FinFET,” IEEE Trans. on Electron Devices, vol. 48, pp.880-886, May 2001.
[15] L. Chang, K. J. Yang, Y.-C. Yeo, Y.-K. Choi, T.-J. King, and C. Hu, “Reduction of direct-tunneling gate leakage current in double-gate and ultra-thin body MOSFETs,” in IEDM Tech. Dig., 2001, pp.99-102.
[16] F.-L. Yang, H.-Y. Chen, F.-C. Chen, Y.-L. Chan, K.-N. Yang, C.-J. Chen, H.-J. Tao, Y.-K. Choi, M.-S. Liang, and C. Hu, “35nm CMOS FinFETs,” in Symp. on VLSI Tech., 2002, pp.104-105.
[17] B. Yu, L. Chang, S. Ahmed, H. Wang, S. Bell, C.-Y. Yang, C. Tabery, C. Ho, Q. Xiang, T.-J. King, J. Bokor, C. Hu, M.-R. Lin, and D. Kyser, “FinFET scaling to 10nm gate length,” in IEDM Tech. Dig., 2002, pp.251-254.
[18] F.-L. Yang, H.-Y. Chen, F.-C. Chen, C.-C. Huang, C.-Y. Chang, H.-K. Chiu, C.-C. Lee, C.-C. Chen, H.-T. Huang, C.-J. Chen, H.-J. Tao, Y.-C. Yeo, M.-S. Liang, and C. Hu, “25 nm CMOS Omega FETs,” in IEDM Tech. Dig., 2002, pp.255-258.
[19] Y.-K. Choi, L. Chang, P. Ranade, J.-S. Lee, D. Ha, S. Balasubramanian, A. Agarwal, M. Ameen, T.-J. King, and J. Bokor, “FinFET Process Refinements for improved mobility and gate work function engineering,” in IEDM Tech. Dig., 2002, pp.259-262.
[20] A. Chatterjee, R. A. Chapman, G. Dixit, J. Kuehne, S. Hattangady, H. Yang, G. A. Brown, R. Aggarwal, U. Erdogan, Q. He, M. Hanratty, D. Rogers, S. Murtaza, S. J. Fang, R. Kraft, A. L. P. Rotondaro, J. C. Hu, M. Terry, W. Lee, C. Fernando, A. Konecni, G. Wells, D. Frystak, C. Bowen, M. Rodder, and I.-C. Chen, “Sub-100nm gate length metal gate NMOS transistors fabricated by a replacement gate process,” in IEDM Tech. Dig., 1997, pp.821-824.
[21] A. Chatterjee, R. A. Chapman, K. Joyner, M. Otobe, S. Hattangady, M. Bevan, G. A. Brown, H. Yang,Q. He, D. Rogers, S.J. Fang, R. Kraft, A. L. P. Rotondaro, M. Terry, K. Brennan, S.-W. Aur, J. C. Hu, H.-L. Tsai, P. Jones, G. Wilk, M. Aoki, M. Rodder, and I.-C. Chen, “CMOS metal replacement gate transistors using tantalum pentoxide gate insulator,” in IEDM Tech. Dig., 1998, pp.777-780.
[22] A. Yagishita, T. Saito, K. Nakajima, S. Inumiya, Y. Akasaka, Y. Ozawa, G. Minamihaba, H. Yano, K. Hieda, K. Suguro, T. Arikado, and K. Okumura, “High performance metal gate MOSFETs fabricated by CMP for 0.1μm regime,” in IEDM Tech. Dig., 1998, pp.785-788.
[23] A. Yagishita, T. Saito, K. Nakajima, S. Inumiya, Y. Akasaka, Y. Ozawa, K. Hieda, Y. Tsunashima, K. Suguro, T. Arikado, and K. Okumura, “High performance damascene metal gate MOSFET’s for 0.1μm regime,” IEEE Trans. on Electron Devices, vol.47, no.5, pp.1028-1034, May 2000.
[24] S. Matsuda, H. Yamakawa, A. Azuma, and Y. Toyoshima, “Performance improvement of metal gate CMOS technologies,” in Symp. on VLSI Tech., 2001, pp.63-64.
[25] F. Ducroquet, H. Achard, F. Coudert, B. Previtali, J.-F. Lugand, L. Ulmer, T. Farjot, Y. Gobil, M. Heitzmann, S. Tedesco, M.-E. Nier, and S. Deleonibus, “Full CMP integration of CVD TiN damascene sub-0.1-μm metal gate devices for ULSI applications,” IEEE Trans. on Electron Devices, vol.48, no.8, pp.1816-1821, Aug. 2001.
[26] K. Matsuo, T. Saito, A. Yagishita, T. Iinuma, A. Murakoshi, K. Nakajima, S. Omoto, and K. Suguro, “Damascene metal gate MOSFETs with Co silicided source/drain and high-k gate dielectrics,” in Symp. on VLSI Tech., 2000, pp.70-71.
[27] I. Polishchuk, P. Ranade, T.-J. King, and C. Hu, “Dual work function metal gate CMOS technology using metal interdiffusion,” IEEE Electron Device Letters, vol.22, no.9, pp.444-446, Sep. 2001.
[28] I. Polishchuk, P. Ranade, T.-J. King, and C. Hu, “Dual work function metal gate CMOS transistors by Ni-Ti interdiffusion,” IEEE Electron Device Letters, vol.23, no.4, pp.200-202, April 2002.
[29] P. Ranade, Y.-C. Yeo, Q. Lu, H. Takeuchi, T.-J. King, and C. Hu, “Molybdenum as a gate electrode for deep sub-micron CMOS technology,” in Mat. Res. Soc. Symp., vol.611, 2000, pp.C3.2.1-C3.2.6.
[30] Q. Lu, R. Lin, P. Ranade, T.-J. King, C. Hu, “Metal gate work function adjustment for future CMOS technology,” in Symp. on VLSI Tech., 2001, pp.45-46.
[31] R. Lin, Q. Lu, P. Ranade, T.-J. King, C. Hu, “An adjustable work function technology using Mo gate for CMOS devices,” IEEE Electron Device Letters, vol.23, no.1, pp.49-51, Jan. 2002.
[32] P. Ranade, Y.-K. Choi, D. Ha, A. Agarwal, M. Ameen, and T.-J. King, “Tunable work function molybdenum gate technology for FDSOI-CMOS,” in IEDM Tech. Dig., 2002, pp.363-366.
[33] M. Qin, Vincent M. C. Poon, and Stephen C. H. Ho, “Investigation of polycrystalline nickel silicide films as a gate material,” Journa of the Electrochemical Society, 148(5), p. G271-G274, 2001.
[34] J. Kedzierski, E. Nowak, T. Kanarsky, Y. Zhang, D. Boyd, R. Carruthers, C. Cabral, R. Amos, C. Lavoie, R. Roy, J. Newbury, E. Sullivan, J. Benedict, P. Saunders, K. Wong, D. Canaperi, M. Krishnan, K. –L. Lee, Beth A. Rainey, D. Fried, P. Cottrell, H. –S. Philip Wong, M. Ieong, and W. Haensch, “Metal-gate FinFET and full-depleted SOI devices using total gate silicidation,” in IEDM Tech. Dig., 2002, pp.247-250.
[35] W. P. Maszara, Z. Krivokapic, P. King, J.-S. Goo, and M.-R. Lin, “Transistors with dual work function metal gates by single full silicidation (FUSI) of polysilicon gates,” in IEDM Tech. Dig., 2002, pp.367-370.
[36] J. H. Sim, H. C. Wen, J. P. Lu, and D. L. Kwong, “Dual work function metal gates using full nickel silicidation of doped poly-Si,” IEEE Electron Device Letters, vol. 24, pp.631-633, Oct. 2003.
[37] J. Yuan and Jason C. S. Woo, “Tunable work function in fully nickel-silicided polysilicon gates for metal gate MOSFET applications,” IEEE Electron Device Letters, vol. 26, pp.87-89, Feb. 2005.
[38] C. Cabral, Jr. J. Kedzierski, B. Linder, S. Zafar, V. Narayanan, S. Fang, A. Steegen, P. Kozlowski, R. Carruthers, and R. Jammy, “Dual workfunction fully silicided metal gates,” in Symp. on VLSI Tech., 2004, pp.184-185.
[39] J. R. Hauser and K. Ahmed, “Characterization of ultra-thin oxides using electrical C-V and I-V measurements,” in Characterization and Metrology for ULSI Technology: 1998 International Conference, 1998, pp.235-239.
[40] K. Yang, Y.-C. King, and C. Hu, “Quantum effect in oxide thickness determination from capacitance measurement,” in Symp. on VLSI Tech., 1999, pp.77-78.

Chapter 2
[1] E. M. Vogel, K. Z. Ahmed, B. Hornung, W. K. Hensen, P. K. McLarty, G. Lucovsky, J. R. Hauser, and J. Wortman, “Modeled tunnel currents for high dielectric constant dielectrics,” IEEE Trans. on Electron Devices, vol.45, pp.1350-1355, June 1998.
[2] Q. Lu, D. Park, A. Kalnitsky, C. Chang, C. –C. Cheng, S. P. Tay, T. –J. King, and C. Hu, “Leakage current comparison between ultra-thin Ta2O5 films and conventional gate dielectrics,” IEEE Electron Device Letters, vol.19, pp.341-342, Sept. 1998.
[3] K. F. Schuegraf, C. C. King, and C. Hu, “Impact of polysilicon depletion in thin oxide MOS technology,” in Proc. Tech. Papers 1993 Int. Symp. VLSI Technology, Systems, and Applications, 1993, pp.86-90.
[4] James R. Pfiester, Frank K. Baker, Thomas C. Mele, H. H. Tseng, Philip J. Tobin, James D. Hayden, James W. Miller, Craig D. Gunderson, and Louis C. Parrillo, “The effects of boron penetration on p+ polisilicon gated PMOS devices,” IEEE Trans. on Electron Devices, vol.37, no.8, pp.1842-1851, August 1990.
[5] H. F. Luan, B. Z. Wu, L. G. Kang, R. Vrtis, D. Roberts, and D. L. Kwong, “Ultra thin high quality Ta2O5 gate dielectric prepared by in-situ rapid thermal processing,” in IEDM Tech. Dig., 1998, pp.609-612.
[6] C. H. Lee, H. F. Luan, W. P. Bai, S. J. Lee, T. S. Jeon, Y. Senzaki, D. Roberts, and D. L. Kwong, “MOS characteristics of ultra thin rapid thermal CVD ZrO2 and Zr silicate gate dielectrics,” in IEDM Tech. Dig., 2000, pp.27-30.
[7] Leland Chang, Stephen Tang, T. J. King, Jeffrey Bokor, and C. Hu, “Gate length scaling and threshold voltage control of double-gate MOSFETs,” in IEDM Tech. Dig., 2000, pp.719-722.
[8] Qiang Lu, Y. C. Yeo, Pushkar Ranade, Hideki Takeuchi, T. J. King, and C. Hu, “Dual-metal gate technology for deep-submicron CMOS transistors,” in Symp. on VLSI Tech., 2000, pp.72-73.
[9] Huicai Zhong, Shin-Nam Hong, You-Seok Suh, Heather Lazar, Greg Heuss, and Veena Misra, “Properties of Ru-Ta alloys as gate electrodes for NMOS and PMOS silicon devices,” in IEDM Tech. Dig., 2001, pp.467-480.
[10] JaeHoon Lee, Huicai Zhong, You-Seok Suh, Greg Heuss, Jason Gurganus, Bei Chen, and Veena Misra, “Tunable work function dual metal gate technology for bulk and non-bulk CMOS,” in IEDM Tech. Dig., 2002, pp.359-362.
[11] Bing-Yue Tsui and Chih-Feng Huang, “Wide range work function modulation of binary alloys for MOSFET application,” IEEE Electron Device Letters, vol.24, pp.153-155, March 2003.
[12] S. H. Bae, W. P. Bai, H. C. Wen, S. Mathew, L. K. Bera, N. Balasubramanian, N. Yamada, M. F. Li, and D. L. Kwong, “Laminated metal gate electrode with tunable work function for advanced CMOS,” in Symp. on VLSI Tech., 2004, pp.188-189.
[13] Pushkar Ranade, Yang-Kyu Choi, Daewon Ha, Aditya Agarwal, Michael Ameen, and Tsu-Jae King, “Tunable work function molybdenum gate technology for FDSOI-CMOS,” in IEDM Tech. Dig., 2002, pp.363-366.
[14] K. J. Yang, Y. -C. King, and C. Hu, “Quantum effect in oxide thickness determination from capacitance measurement,” in Symp. on VLSI Tech., 1999, pp.77-78.
[15] P. Ranade, Y. C. Yeo, Q. Lu, H. Takeuchi, T-J. King, and C. Hu, “Molybdenum metal gate MOS technology for post-SiO2 gate dielectrics,” in Mat. Res. Soc. Symp., vol.611, 2000, pp.C3.2.1-C3.2.6.
[16] A. Yagishita, T. Saito, K. Nakajima, S. Inumiya, Y. Akasaka, Y. Ozawa, G. Minamihaba, H. Yano, K. Hieda, K. Suguro, T. Arikado, and K. Okumura, “High performance metal gate MOSFETs fabricated by CMP for 0.1�慆 regime,” in IEDM Tech. Dig., 1998, pp.785-788.
[17] C. D. Gelatt Jr., and H. Ehrenreich, “Charge transfer in alloys: AgAu,” Phys. Rev. B, vol. 10, no. 2, pp.398-415, July 1974.
[18] C. Kittel, Introduction to Solid State Physics, 7th ed. New York: Wiley, 1996, pp.151-157.
[19] Massalski Thaddeus B. ed., Binary Alloy Phase Diagrams, Metal Park, Ohio: American Society for Metals, 1990, pp.2088-2089.

Chapter 3
[1] R. Beyers, “Thermaldynamic considerations in refractory metal-silicon- oxygen systems,” Journal of Applied Physics, 56(1), pp. 147-152, 1 July 1984.
[2] P. Ranade, Y. C. Yeo, Q. Lu, H. Takeuchi, T-J. King, and C. Hu, “Molybdenum metal gate MOS technology for post-SiO2 gate dielectrics,” in Mat. Res. Soc. Symp., vol.611, 2000, pp.C3.2.1-C3.2.6.
[3] Pushkar Ranade, Yang-Kyu Choi, Daewon Ha, Aditya Agarwal, Michael Ameen, and Tsu-Jae King, “Tunable work function molybdenum gate technology for FDSOI-CMOS,” in IEDM Tech. Dig., 2002, pp.363-366.
[4] Veena Misra, Greg P. Heuss, and Huicai Zhong, “Use of metal-oxide- semiconductor capacitors to detect interactions of Hf and Zr gate electrodes with SiO2 and ZrO2,” Applied Physics Letters, vol.78, no.26, pp.4166-4168, 25 June 2001.
[5] A. Yagishita, T. Saito, K. Nakajima, S. Inumiya, Y. Akasaka, Y. Ozawa, G. Minamihaba, H. Yano, K. Hieda, K. Suguro, T. Arikado, and K. Okumura, “High performance metal gate MOSFETs fabricated by CMP for 0.1μm regime,” in IEDM Tech. Dig., 1998, pp.785-788.

Chapter 4
[1] “International Technology Roadmap for Semiconductors—Front-End Process,” Semiconductor Industry Association, 2004.
[2] E. M. Vogel, K. Z. Ahmed, B. Hornung, W. K. Hensen, P. K. McLarty, G. Lucovsky, J. R. Hauser, and J. Wortman, “Modeled tunnel currents for high dielectric constant dielectrics,” IEEE Trans. on Electron Devices, vol.45, pp.1350-1355, June 1998.
[3] Q. Lu, D. Park, A. Kalnitsky, C. Chang, C. –C. Cheng, S. P. Tay, T. –J. King, and C. Hu, “Leakage current comparison between ultra-thin Ta2O5 films and conventional gate dielectrics,” IEEE Electron Device Letters., vol.19, pp.341-342, Sept. 1998.
[4] B. Cheng, M. Cao, R. Rao, A. Inani, P. V. Voorde, W. M. Greene, J. M. C. Stork, Z. Yu, P. M. Zeitzoff, and J. C. S. Woo, “The impact of high-k gate dielectrics and metal gate electrodes on sub-100 nm MOSFET’s,” IEEE Trans. on Electron Devices, vol.46, pp.1537-1544, July 1999.
[5] Y. Abe, T. Oishi, K. Shiozawa, Y. Tokuda, and S. Satoh, “Simulation study on comparison between metal gate and polysilicon gate for sub-quarter-micron MOSFET’s,” IEEE Electron Device Letters, vol.20, pp.632-634, Dec. 1999.
[6] Leland Chang, Stephen Tang, T. J. King, Jeffrey Bokor, and C. Hu, “Gate length scaling and threshold voltage control of double-gate MOSFETs,” in IEDM Tech. Dig., 2000, pp.719-722.
[7] Qiang Lu, Y. C. Yeo, Pushkar Ranade, Hideki Takeuchi, T. J. King, and C. Hu, “Dual-metal gate technology for deep-submicron CMOS transistors,” in Symp. on VLSI Tech., 2000, pp.72-73.
[8] M. Qin, Vincent M. C. Poon, and Stephen C. H. Ho, “Investigation of polycrystalline nickel silicide films as a gate material,” Journa of the Electrochemical Society, 148(5), pp.G271-G274, 2001.
[9] J. Kedzierski, E. Nowak, T. Kanarsky, Y. Zhang, D. Boyd, R. Carruthers, C. Cabral, R. Amos, C. Lavoie, R. Roy, J. Newbury, E. Sullivan, J. Benedict, P. Saunders, K. Wong, D. Canaperi, M. Krishnan, K.-L. Lee, Beth A. Rainey, D. Fried, P. Cottrell, H.-S. Philip Wong, M. Ieong, and W. Haensch, “Metal-gate FinFET and full-depleted SOI devices using total gate silicidation,” in IEDM Tech. Dig., 2002, pp.247-250.
[10] W. P. Maszara, Z. Krivokapic, P. King, J. –S. Goo, and M. –R. Lin, “Transistors with dual work function metal gates by single full silicidation (FUSI) of polysilicon gates,” in IEDM Tech. Dig., 2002, pp.367-370.
[11] J. H. Sim, H. C. Wen, J. P. Lu, and D. L. Kwong, “Dual work function metal gates using full nickel silicidation of doped poly-Si,” IEEE Electron Device Letters, vol.24, pp.631-633, Oct. 2003.
[12] J. Yuan and Jason C. S. Woo, “Tunable work function in fully nickel-silicided polysilicon gates for metal gate MOSFET applications,” IEEE Electron Device Letters, vol.26, pp.87-89, Feb. 2005.
[13] C. Cabral, Jr. J. Kedzierski, B. Linder, S. Zafar, V. Narayanan, S. Fang, A. Steegen, P. Kozlowski, R. Carruthers, and R. Jammy, “Dual workfunction fully silicided metal gates,” in Symp. on VLSI Tech., 2004, pp.184-185.
[14] Pushkar Ranade, Yang-Kyu Choi, Daewon Ha, Aditya Agarwal, Michael Ameen, and Tsu-Jae King, “Tunable work function molybdenum gate technology for FDSOI-CMOS,” in IEDM Tech. Dig., 2002, pp.363-366.
[15] R. Beyers, “Thermaldynamic considerations in refractory metal-silicon- oxygen systems,” Journal of Applied Physics, 56(1), pp.147-152, 1 July 1984.
[16] K. J. Yang, Y. -C. King, and C. Hu, “Quantum effect in oxide thickness determination from capacitance measurement,” in Symp. on VLSI Tech., 1999, pp.77-78.
[17] Ronald. Lin, Q. Lu, P. Ranade, T. –J. King, and C. Hu, “An adjustable work function technology using Mo gate for CMOS devices,” IEEE Electron Device Letters, vol.23, pp.49-51, Jan. 2002.
[18] J. M. Liang and L. J. Chen, “Interfacial reactions and thermal stability of ultrahigh vacuum deposited multilayered Mo/Si structures,” Journal of Applied Physics, 79(8), pp.4072-4077, 15 April 1996.
[19] J. F. Moulder, W. F. Stickle, P. E. Sobol, K. D. Bomben, edited by Jill Chastain, Handbook of X-ray photoelectron spectroscopy, Perkin-Elmer Corporation, Minnesota: Physical Electronics Division, 1992.
[20] J. M. Slaughter, Arye Shapiro, Patrick A. Kearney, and Charles M. Falco, “Growth of molybdenum on silicon: Structure and interface formation,” Phys. Rev. B, vol.44, no.2, pp.3854-3863, 1991.
[21] Naoya Ohishi, Hideto Yanagisawa, Katsutaka Sasaki, and Yoshio Abe, “Initial silicide formation process of Mo/(100) Si system prepared using an ultrahigh-vacuum sputtering system,” Electronics and Communications in Japan, Part 2: Electronics, vol.84, no.3, pp.71-78, 2001.

Chapter 5
[1] E. M. Vogel, K. Z. Ahmed, B. Hornung, W. K. Hensen, P. K. McLarty, G. Lucovsky, J. R. Hauser, and J. Wortman, “Modeled tunnel currents for high dielectric constant dielectrics,” IEEE Trans. on Electron Devices, vol.45, pp.1350-1355, June 1998.
[2] Q. Lu, D. Park, A. Kalnitsky, C. Chang, C. –C. Cheng, S. P. Tay, T. –J. King, and C. Hu, “Leakage current comparison between ultra-thin Ta2O5 films and conventional gate dielectrics,” IEEE Electron Device Letters, vol.19, pp.341-342, Sept. 1998.
[3] H. F. Luan, B. Z. Wu, L. G. Kang, R. Vrtis, D. Roberts, and D. L. Kwong, “Ultra thin high quality Ta2O5 gate dielectric prepared by in-situ rapid thermal processing,” in IEDM Tech. Dig., 1998, pp.609-612.
[4] C. H. Lee, H. F. Luan, W. P. Bai, S. J. Lee, T. S. Jeon, Y. Senzaki, D. Roberts, and D. L. Kwong, “MOS characteristics of ultra thin rapid thermal CVD ZrO2 and Zr silicate gate dielectrics,” in IEDM Tech. Dig., 2000, pp.27-30.
[5] J. H. Sim, H. C. Wen, J. P. Lu, and D. L. Kwong, “Dual work function metal gates using full nickel silicidation of doped poly-Si,” IEEE Electron Device Letters, vol.24, pp.631-633, Oct. 2003.
[6] J. Yuan and Jason C. S. Woo, “Tunable work function in fully nickel-silicided polysilicon gates for metal gate MOSFET applications,” IEEE Electron Device Letters, vol.26, pp.87-89, Feb. 2005.
[7] T. Nabatame, M. Kadoshima, K. Iwamoto, N. Mise, S. Migita, M. Ohno, H. Ota, N. Yasuda, A. Ogawa, K. Tominaga, H. Satake, and A. Toriumi, “Partial silicides technology for tunable work function electrodes on high-k gate dielectrics─Fermi level pinning controlled PtSix for HfOx(N) pMOSFET─,” in IEDM Tech. Dig., 2004, pp.83-86.
[8] C.Hobbs, L. Fonseca, V. Dhandapani, S. Samavedam, B. Taylor, J. Grant, L. Dip, D. Triyoso, R. Hegde, D. Gilmer, R. Garcia, D. Roan, L. Lovejoy, R. Rai, L. Hebert, H. Tseng, B. White, and P. Tobin, “Fermi level pinning at the PolySi/metal oxide interface,” in Symp. on VLSI Tech., 2003, pp.09-10.
[9] E. Cartier, V. Narayanan, E. P. Gusev, P. Jamison, B. Linder, M. Steen, K. K. Chan, M. Frank, N. Bojarczuk, M. Copel, S. A. Cohen, S. Zafar, A. Callegari, M. Gribelyuk, M. P. Chudzik, C. Cabral Jr., R. Carruthers, C. D’Emic, J. Newbury, D. Lacey, S. Guha, and R. Jammy, “Systematic study of pFET Vt with Hf-based gate stacks with poly-Si and FUSI gates,” in Symp. on VLSI Tech., 2004, pp.44-45.
[10] M. Koyama, Y. Kamimuta, T. Ino, A. Kaneko, S. Inumiya, K. Eguchi, M. Takayanagi, and A. Nishiyama, “Careful examination on the asymmetric Vfb shift problem for poly-Si/HfSiON gate stack and its solution by the Hf concentration control in the dielectric near the poly-Si interface with small EOT expense,” in IEDM Tech. Dig., 2004, pp.499-502.
[11] E. P. Gusev, C. Cabral Jr., B. P. Linder, Y. H. Kim, K. Maitra, E. Cartier, H. Nayfeh, R. Amos, G. Biery, N. Bojarczuk, A. Callegari, R. Carruthers, S. A. Cohen, M. Copel, S. Fang, M. Frank, S. Guha, M. Gribelyuk, P. Jamison, R. Jammy, M. Ieong, J. Kedzierski, P. Kozlowski, V. Ku, D. Lacey, D. LaTulipe, V. Narayanan, H. Ng, P. Nguyen, J. Newbury, V. Paruchuri, R. Rengarajan, G. Shahidi, A. Steegen, M. Steen, S. Zafar, and Y. Zhang, “Advanced gate stacks with fully silicided (FUSI) gates and high-k dielectrics: enhanced performance at reduced gate leakage,” in IEDM Tech. Dig., 2004, pp.79-82.
[12] K. G. Anil, A. Veloso, S. Kubicek, T. Schram, E. Augendre, J. –F. de Marneffe, K. Devriendt, A. Lauwers, S. Brus, K. Hensen, and S. Biesemans, “Demonstration of fully Ni-silicided metal gates on HfO2 based high-k gate dielectrics as a candidate for low power applications,” in Symp. on VLSI Tech., 2004, pp.190-191.
[13] M. Kadoshima, A. Ogawa, M. Takahashi, H. Ota, N. Mise, K. Iwamoto, S. Migita, H. Fujiwara, H. Satake, T. Nabatame, and A. Toriumi, “Fermi level pinning engineering by Al compositional modulation and doped partial silicide for HfAlOx(N) CMOSFETs,” in Symp. on VLSI Tech., 2005, pp.70-71.
[14] C. S. Park, B. J. Cho, L. J. Tang, and D. –L. Kwong, “Substituted aluminum metal gate on high-k dielectric for low work function and Fermi-level pinning free,” in IEDM Technical Digest, 2004, pp.299-302.
[15] M. Terai, K. Takahashi, K. Manabe, T. Hase, T. Ogura, M. Saitoh, T. Iwamoto, T. Tatsumi, and H. Watanabe, “Highly reliable HfSiON CMOSFET with phase controlled NiSi (NFET) and Ni3Si (PFET) FUSI gate electrode,” in Symp. on VLSI Tech., 2005, pp.68-69.
[16] J. A. Kittl, A. Veloso, A. Lauwers, K. G. Anil, C. Demeurisse, S. Kubicek, M. Niwa, M. J. H. van Dal, O. Richard, M. A. Pawlak, M. Jurczak, C. Vrancken, T. Chiarella, S. Brus, K. Maex, and S. Biesemans, “Scalability of Ni FUSI gate processes: phase and Vt control to 30nm gate lengths,” in Symp. on VLSI Tech., 2005, pp.72-73.
[17] K. J. Yang, Y. -C. King, and C. Hu, “Quantum effect in oxide thickness determination from capacitance measurement,” in Symp. on VLSI Tech., 1999, pp.77-78.
[18] J. H. Lee, Y. –S. Suh, H. Lazar, R. Jha, J. Gurganus, Y. Lin, and V. Misra, “Compatibility of dual metal gate electrodes with high-k dielectrics for CMOS,” in IEDM Tech. Dig., 2003, pp.323-326.