臺灣博碩士論文加值系統

電纜放電(Cable Discharge Event, CDE)已是造成網路介面積體電路損傷的主要原因。而在靜電放電(Electrostatic Discharge, ESD)防護元件之耐受能力測試中，傳輸線脈衝產生系統(Transmission Line Pulsing System, TLP)是觀測元件在靜電轟擊下電性特徵最重要的方法。一方面為了解電纜放電防護元件之物理特性，另一方面更能在晶片製作完成之初，能先了解產品之電纜放電的承受能力。於是本篇論文利用架設的長脈衝傳輸線脈衝產生系統去模擬電纜放電對測試元件的影響，並用來量測和分析電纜放電防護元件之二次崩潰特性，然後再與傳統的傳輸線脈衝產生系統進行比較。透過新提出的長脈衝傳輸線脈衝系統(Long-Pulse Transmission Line Pulsing System, LP-TLP)和傳統的傳輸線脈衝產生系統對元件進行測試後，發現元件對電纜放電耐受度比起人體放電模式(Human Body Model, HBM)靜電放電耐受度明顯降低。

Cable discharge event (CDE) has been the main cause which damages the Ethernet interface. The transmission line pulsing (TLP) system has been the most important method to observe the electric characteristics of the device under human-body-model (HBM) ESD stress. To understand the physical characteristics and CDE robustness of protection device in the wafer level, the long-pulse transmission line pulsing (LP-TLP) system has been set up and used to simulate the influence of CDE on the Ethernet integrated circuits and to measure and analyze the secondary breakdown characteristics of the CDE protection devices. Furthermore, the measured results by using the LP-TLP system are compared with those by using the traditional 100-ns TLP system. The experimental results have shown that the CDE robustness of NMOS and PMOS devices in deep-submicron CMOS technology is much worse than their HBM ESD robustness.

CONTENTS
ABSTRACT (CHINESE) i
ABSTRACT (ENGLISH) iii
ACKNOWLEDGEMENT vi
CONTENTS vii
TABLE CAPTIONS ix
FIGURE CAPTIONS x
Chapter 1 Introduction 1
1.1 BACKGROUND 1
1.2 THESIS ORGANIZATION 2
Chapter 2 Cable Discharge Test 5
2.1 CDE IN ETHERNET LOCAL AREA NETWORK 5
2.2 DISCHARGE BETWEEN LAN CABLING AND EQUIPMENT 6
2.3 SUMMARY 7
Chapter 3 Long-Pulse TLP (LP-TLP) Measurement Setup 13
3.1 TRADITIONAL TRANSMISSION LINE PULSING (TLP) SYSTEM 13
3.2 NEW LONG-PULSE TRANSMISSION LINE PULSING (LP-TLP) SYSTEM 13
3.2.1 Measurement setup of the proposed LP-TLP 13
3.2.2 Verification on LP-TLP with a Load of 50-W Resistor 15
3.2.3 Verification on Gate-Grounded NMOS (GGNMOS) 15
3.3 SUMMARY 16
Chapter 4 Dependence of Layout Parameters on CDE Robustness of CMOS Devices 25
4.1 NMOS/PMOS IN A 0.25-mm SALICIDED CMOS PROCESS 25
4.1.1 Channel Width 26
4.1.2 Channel Length 27
4.1.3 Unit-Finger Width 28
4.1.4 Spacing from Source Contact to Poly-Gate Edge 29
4.1.5 SAB Width 30
4.1.6 Failure Analysis 31
4.2 NMOS/PMOS IN A 0.18-mm SALICIDED CMOS PROCESS 32
4.2.1 Clearance from SAB to Poly-Gate Edge 32
4.2.2 Distance from drain diffusion to Guard Ring Edge 33
4.3 COMPARISON BETWEEN 0.25-mm AND 0.18-mm CMOS PROCESSES 34
4.4 SCR DEVICE IN A 0.18-mm CMOS PROCESS 35
4.4.1 Lateral SCR (LSCR) 36
4.4.2 Modified Lateral SCR (MLSCR) 37
4.5 APPLICATION OF LP-TLP SYSTEM 38
4.6 SUMMARY 41
Chapter 5 Conclusions and Future Works 60
5.1 MAIN RESULTS OF THIS THESIS 60
5.2 FUTURE WORKS 61
REFERENCES 62
VITA 64

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