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研究生:胡芳綾
研究生(外文):Fang-Ling, Hu
論文名稱:具有電壓迴轉率控制之混合式電壓輸入/輸出緩衝器設計
論文名稱(外文):Mixed-Voltage I/O Buffers with Slew-Rate Control in Nanoscale CMOS Processes
指導教授:柯明道柯明道引用關係
指導教授(外文):Ming-Dou, Ker
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電子工程系所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2006
畢業學年度:94
語文別:英文
論文頁數:116
中文關鍵詞:混合電壓輸入/輸出緩衝器熱載子電壓迴轉率接地彈跳
外文關鍵詞:Mixed-voltage I/O bufferHot-carrierSlew-rateGround bounce
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隨著製程的進步,電晶體所能承受的最大節點電壓,包括閘極-源極電壓 (Vgs),閘極-汲極電壓 (Vgd) 及汲極-源極電壓 (Vds),必須隨著變小以確保電路有足夠大的生存時間。此外電路的操作速度越來越快,使得接地彈跳 (ground bounce) 越來越嚴重,影響電路的操作表現變差。
在微電子系統中,以較早的CMOS製程技術所設計的電路,使用相對於先進製程所能容忍的較大工作電壓。因此在傳輸介面上,以先進製程設計的晶片可能會接收比它正常工作電壓更大的電壓訊號。而混合電壓輸出入緩衝器 (mixed-voltage I/O buffers) 普遍的應用在傳輸介面上,在確保生存時間的情況下接收較高電壓的訊號,並且以較低的操作電壓工作來達到高速、低功率的電路需求。而在製程中使用具較薄閘極氧化層 (gate-oxide) 的電晶體來設計混合電壓輸出入緩衝器可以有較低的成本、較短的電路製造時間以及較高的操作速度。雖然這樣的混合電壓輸出入緩衝器在傳送及接收模式下,不會遭受到閘極氧化層劣化 (gate-oxide degradation) 、熱載子效應 (hot-carrier effect) 的問題,但是當電路在接收高電壓訊號模式轉換為傳送模式的過程,電晶體可能會因熱載子效應劣化。在深次微米製程下,電晶體通道越來越短,使得電場強度變強,因而熱載子效應更加嚴重,成為設計穩定可靠電路的重要議題之一。
在本篇論文當中,提出了兩個混壓電路設計,無論在接收、傳送模式,或是接收轉傳送的過程都不會有閘極氧化層劣化及熱載子效應的問題。其中一個電路具有抑制熱載子效應的電路,並且可以維持原本電路的電流驅動能力。另一個則是應用阻絕的NMOS電晶體 (blocking NMOS) 來避免熱載子效應造成劣化。此兩電路以0.18-�慆 1P6M CMOS製程技術實現,操作速度高至266 MHz,並且接收1.5-V/3.3-V輸入訊號,傳送1.5-V輸出訊號,可與具PCI-X 2.0規格應用相容。
在論文最後,提出在混壓介面電路上的控制電壓迴轉率 (slew-rate control)的電路設計。這樣的電路設計可以幫助改善在電源線上的接地彈跳效應,藉此達到較高表現的高速輸出入電路設計 (high speed I/O circuit)。此外,進一步改善接地彈跳效應的電路設計技巧在此篇論文中做了討論及整理。
Transistors fabricated with thin gate oxides are vulnerable to dielectric damage and reliability problems due to excessive electric fields. The difference between operating voltage and maximum allowed terminal voltages including gate-source voltage (Vgs), gate-drain voltage (Vgd) and drain-source voltage (Vds) of MOS transistors have decreased drastically with the advancement of CMOS process. Also, the ground bounce effects get worse with increasing operating speed. These present special challenges for I/O designers.
With compatibility to the earlier defined standards or interface protocols of CMOS ICs in a microelectronics system, the chips fabricated in the advanced CMOS processes will face to the interface of input signals with voltage levels higher than their normal supply voltage (VDD). As a result, mixed-voltage I/O buffers with only thin-oxide devices have been designed with advantages of less fabrication time in process, less cost and higher operating speed to communicate the advanced circuits with the earlier ones. Although such mixed-voltage I/O buffers have overcome several problems, such as gate-oxide reliability [1], hot-carrier degradation [2], and the undesired circuit leakage paths between chips [3], in receive mode and transmit mode, they often suffer from hot-carrier degradation during the transition from receiving high-level voltage to transmitting low-level voltage. The hot-carrier induced degradation, however, becomes one of the most important reliability concerns since the MOSFET devices feature extremely short channel length and high electric field in the nano-meter CMOS technologies.
In this thesis, two mixed-voltage I/O buffers realized with only thin-oxide devices to receive 2xVDD-tolerant input signals without suffering the hot-carrier reliability issue are proposed. The mixed-voltage I/O buffer using two-stacked NMOS transistors are designed with new proposed hot-carrier prevented circuit. In this design, the driving capacity will be sustained. The other I/O buffer is designed with two blocking NMOS devices and dynamic gate-controlled circuit to overcome gate-oxide reliability problem and hot-carrier degradation. These two I/O buffers have been fabricated in a 0.18-�慆 1P6M CMOS process. From experimental results, the fabricated 2xVDD-tolerant I/O buffers can support the operating speed of up to 266 MHz, which can meet the applications of PCI-X 2.0.
Furthermore, the mixed-voltage I/O buffers with slew-rate control are proposed to reduce ground bounce and achieve high circuit performance in high-speed interfaces. The design based on the mixed-voltage I/O buffer with blocking NMOS devices and dynamic gate-controlled circuit has been fabricated in a 0.18-�慆 1P6M CMOS process. The other circuit techniques to further reduce ground bounce are also introduced in last part of the thesis.
ABSTRACT (CHINESE) i
ABSTRACT (ENGLISH) iii
ACKNOWLEDGEMENT v
TABLE CAPTIONS ix
FIGURE CAPTIONS x
Chapter 1 Introduction 1
1.1 MOTIVATION 1
1.2 MIXED-VOLTAGE I/O BUFFERS 2
1.3 HOT-CARRIER EFFECT 5
1.3.1 The Mechanism of Hot-Carrier Effect 6
1.3.2 Hot-Carrier-Induced Lifetime Issue 8
1.3.3 Hot-Carrier Issue in Typical Mixed-Voltage I/O Buffers 9
1.4 BRIEF INTRODUCTION TO PCI-X 2.0 [17] 11
1.5 THESIS ORGANIZATION 11
Chapter 2 Prior Designs on Mixed-Voltage I/O Buffer with a Tolerant Voltage of 2xVDD 13
2.1 PRIOR DESIGN I: A MIXED-VOLTAGE I/O BUFFER WITH GATE-TRACKING CIRCUIT AND DYNAMIC N-WELL BIAS CIRCUIT 13
2.1.1 Design Concept 13
2.1.2 Circuit Description 16
2.1.3 Hot-Carrier Issues in GTCMXIO 18
2.2 PRIOR DESIGN II: A MIXED-VOLTAGE I/O BUFFER WITH BLOCKING NMOS AND DYNAMIC GATE-CONTROLLED CIRCUIT 19
2.2.1 Circuit Description 19
2.2.2 Hot-Carrier Issues in SBNMXIO 22
Chapter 3 Reliability Design on Mixed-Voltage I/O Buffers with Consideration of Hot-Carrier Effect 24
3.1 INTRODUCTION 24
3.2 2XVDD-TOLERANT I/O BUFFER WITH DOUBLE-CASCODE STRUCTURE [14], [25] ……………………………………………………………………………24
3.3 NEW DESIGN I:MIXED-VOLTAGE I/O BUFFER WITH NEW PROPOSED HOT-CARRIER-PREVENTED CIRCUIT 27
3.3.1 Design Concept 27
3.3.2 Circuit Implementation 29
3.3.3 Whole 2xVDD-Tolerant I/O Buffer With Hot-Carrier-Prevented Circuit 31
3.3.4 Simulation Results 33
3.3.5 Summary for Simulation Results 38
3.4 NEW DESIGN II: MIXED-VOLTAGE I/O BUFFER WITH TWO BLOCKING NMOS DEVIES AND DYNAMIC GATE-CONTROLLED CIRCUIT 40
3.4.1 Design Concept 40
3.4.2 Circuit Implementation 42
3.4.3 Simulation Results 44
3.5 EXPERIMENTAL RESULTS 47
3.5.1 Measurement Settings 47
3.5.2 Experimental Results for HCPMXIO 50
3.5.3 Experimental Results for TBNMXIO 54
3.6 DISCCUSION AND SUMMARY 58
3.6.1 Discussion 58
3.6.2 Summary 59
Chapter 4 Mixed-Voltage I/O Buffers with Slew-Rate Control 60
4.1 INTRODUCTION 60
4.2 SLEW-RATE CONTROL IN TYPICAL I/O BUFFERS 61
4.2.1 Conventional Slew-Rate Control 61
4.2.2 Improved slew-rate control to reduce short-circuit current 62
4.3 SLEW-RATE CONTROL ON THE TBNMXIO 63
4.3.1 Circuit Implementation 63
4.3.2 Simulation Results 64
4.3.3 Ground Bounce 67
4.4 SLEW-RATE CONTROL ON THE HCPMXIO 72
4.4.1 Reliability Issues 72
4.4.2 New Slew-Rate Control on Mixed-Voltage I/O Buffer 73
4.4.3 Simulation Results 76
4.5 PRINCIPLES FOR FURTHER REDUCING GROUND BOUNCE 80
4.5.1 Distributed Technique 81
4.5.2 Weighted Technique 83
4.5.3 Separate Power Pad 86
4.6 EXPERIMENTAL RESULTS 88
4.7 DISCUSSION AND SUMMARY 95
4.7.1 Discussion 95
4.7.2 Summary 96
Chapter 5 Conclusion and Future Works 97
5.1 CONCLUSION 97
5.2 FUTRUE WORKS 98
REFERENCES 99
VITA 102
[1] T. Furukawa, D. Turner, S. Mittl, M. Maloney, R. Serafin, W. Clark, L. Longenbach, and J. Howard, “Accelerated gate-oxide breakdown in mixed-voltage I/O buffers,” in Proc. IEEE Int. Reliability Physics Symp., 1997, pp. 169−173.
[2] I.-C. Chen, J. Y. Choi, and C. Hu, “The effect of channel hot-carrier stressing on gate-oxide integrity in MOSFETs,” IEEE Trans. Electron Devices, vol. 35, pp. 2253−2258, Dec. 1988.
[3] S. Voldman, “ESD protection in a mixed voltage interface and multrial disconnected power grid environment in 0.5- and 0.25-μm channel length CMOS technologies,” in Proc. EOS/ESD Symp., 1994, pp. 125−134.
[4] M.-S. Liang, C. Chang. W. Yang, C. Hu and R. W Brodersen, “Hot-carriers induced degradation in thin gate oxide MOSFETs,” in International Electron Devices Meeting (IEDM) Tech. Digest, 1983, pp. 186.
[5] S. Poon, C. Atwell, C. Hart, D. Kolar, C. Lage, and B. Yeargain, “A versatile 0.25 micron CMOS technology,” in IEDM. Tech. Dig., 1998, pp. 751−754.
[6] M. Hargrove, S. Crowder, E. Nowak, R. Logan, L. K. Han, H. Ng, A. Ray, D. Sinitsky, P. Smeys, F. Guarin, J. Oberschmidt, E. Crabb��, D. Yee, and L. Su, “High-performance sub-0.08 μm CMOS with dual gate oxide and 9.7 ps inverter delay,” in IEDM. Tech. Dig., 1998, pp. 627−630.
[7] M. Takahashi, T. Sakurai, K. Sawada, K. Nogami, M. Ichida, and K. Matsuda, “3.3V-5V compatible I/O circuit without thick gate oxide,” in Proc. Of IEEE Custom Integrated Circuits Conference, 1992, pp. 23.3.1-23.3.4.
[8] M. J. M. Pelgrom and E. C. Dijkmans, “A 3/5-V compatible buffer”, IEEE J. Solid-State Circuits, vol.30, pp. 823-825, July 1995.
[9] C.-H. Chuang and M.-D. Ker, “Design on mixed-voltage-tolerant I/O interface with novel tracking circuits in a 0.13-μm CMOS technology.” IEEE Int. Symp. on Circuits and Systems, 2004, vol. 2, pp .577-580.
[10] M.-D. Ker, S.-L. Chen, and C.-S. Tsai, “Design of mixed-voltage I/O buffer with gate-tracking circuit and dynamic n-well bias circuit,” IEEE Trans. On Circuits and Systems I: Regular Paper, in press, 2006.
[11] D. A. Neamen, Semiconductor Physics and Devices – Basic Principles, 3rd ed., New York: McGraw-Hill, 2003.
[12] Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices, New York: Cambridge University Press, 1998.
[13] J. Tanaka, S. Kimura, H. Noda, T. Toyabe, and S. Ihara, “A sub-0.1-�慆 grooved gate MOSFET with high immunity to short-channel effect,” in IEDM. Tech. Dig., 1993, pp. 537-540.
[14] A.-J. Annema, G. J. G. M. Geelen, and P. C. de Jong, “5.5-V I/O in a 2.5-V 0.25-mm CMOS Technology,” IEEE J. Solid-State Circuits, vol. 36, no. 3, pp. 528-538, March 2001.
[15] P. Woerlee, P. Damink, M. van Dort, C. Juffermans, C. de Kort, H. Lifka, W. Manders, G. Paulsen, H. Pomp, J. Slotboom, G. Streutker, and R. Woltjer, “The impact of scaling on hot-carrier degradation and supply voltage of deep-submicron NMOS transistors,” in IEDM. Tech. Dig., 1991, pp. 537−540.
[16] J. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits – A Design Perspective, 2nd ed., Prentice Hall, 2003.
[17] J. Brewer and J. Sekel (2004, Jun.). White paper: PCI Express Technology. Dell Inc., US. [Online]. Available: http://www.dell.com/content/topics/global.aspx
/vectors/en/2004_pciexpress?c=us&l=en&s=corp
[18] M.-D. Ker, S.-L. Chen, and C.-S. Tsai, “Design on mixed-voltage I/O circuit with blocking NMOS and dynamic gate-controlled circuit for high-voltage-tolerant applications,” IEEE Int. Symp. on Circuits and Systems, 2005, pp. 1859-1862.
[19] S. Dabral and T. Maloney, Basic ESD and I/O Design, John Wiley & Sons, 1998.
[20] H.-C. Chow, “Bidirectional buffer for mixed-voltage applications,” in Proc. IEEE Int. Symp. Circuits Syst., 1999, vol. 1, pp. 270−273.
[21] R. D. Adams, R. C. Flaker, K. S. Gray, and H. L. Kalter, “CMOS off-chip driver circuit,” U.S. Patent 4782250, Nov. 1, 1988.
[22] D.-Y. Chen, “Design of a mixed 3.3 V and 5 V PCI I/O buffer,” in Proc. IEEE Int. ASIC Conf., 1996, pp. 336−339.
[23] M.-D. Ker, S.-L. Chen, and C.-S. Tsai, “Design of charge pump circuit with consideration of gate-oxide reliability in low-voltage CMOS processes,” IEEE J. Solid-State Circuits, vol. 41, pp. 1100-1107, May 2006.
[24] M.-D. Ker, C.-Y. Chang, and H.-C. Jiang, “Design of negative charge pump circuit with polysilicon diodes in a 0.25-μm CMOS process,” in Proc. IEEE Asia-Pacific Conf. Advanced System Integrated Circuits, 2002, pp. 145−148.
[25] A. J. Annema, Govert J. G. M. Geelen, “High-voltage level tolerant transistor circuit,” New York, U.S. Patent 6320414B1, Nov. 20, 2001.
[26] M.-D. Ker, S.-L. Chen, and C.-S. Tsai, “Design of charge pump circuit with consideration of gate-oxide reliability in low-voltage CMOS processes,” IEEE J. Solid-State Circuits, vol. 41, pp. 1100-1107, May 2006.
[27] F. Garcia, P. Coll, and D. Auvergne, “Design of a Slew Rate Controlled Output Buffer,” in Proc. IEEE Int. ASIC Conf., 1998, pp. 147−150.
[28] M. S. Haydt, R. Owens, and S. Mourad, “Modeling the Effect of Ground Bounce on Noise Margin,” in Proc. IEEE International Test Conf., Oct. 1994, pp. 279-285.
[29] B. Deutschmann and T. Ostermann, “CMOS output drivers with reduced ground bounce and electromagnetic emission,” in Proc. of European Solid-State Circuits Conf., Sep. 2003, pp. 537-540.
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