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研究生:林庭瑋
研究生(外文):Ting-Wei Lin
論文名稱:多媒體串流處理器之運算單元設計
論文名稱(外文):An ALU Cluster Design for Media Streaming Processors Architecture
指導教授:闕河鳴闕河鳴引用關係
指導教授(外文):Herming Chiueh
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電信工程系所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2005
畢業學年度:94
語文別:英文
論文頁數:59
中文關鍵詞:多媒體串流處理器運算單元
外文關鍵詞:ALU ClusterMedia Streaming Processors Architecturememory bandwidth hierarchylow powerconcurrencylocality
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近期相關的研究已提出利用串流架構來解決多媒體應用在傳統處理器架構上執行的缺點。除此之外,對行動式的系統而言,低功率消耗的考量已變成一個重要的議題,但是目前的串流架構並沒有針對以上的要求去解決。因此,在本研究中提出了將一個多媒體串流架構與數個低功率電路設計的方法結合在一起來解決以上的要求。而本論文的目的是設計一個多媒體串流處理器的運算單元,且基於史丹佛大學所提出的串流處理器架構,在本研究的微架構上考慮了設計的可行性,及利用電腦輔助軟體的模擬結果來決定各個功能單元的架構。並且此架構結合了階層式的頻寬設計,來有效的利用記憶體之間的頻寬。在實驗數據的預估顯示上,針對多媒體應用及基頻通訊系統方面去執行所選定的標準檢查程式,並藉由動態的選擇所要使用的運算單元總數目,可將功率損耗與能量消耗變成可調整式的。因此,對於一個行動式的系統,其即時的效能表現與能量消耗之間的取捨成為可以做最佳化的。所以此提出的架構與相關類似的架構相比之下,已經對有限的電池壽命在功率消耗和執行時間之間提供一個重要的突破。
Recent research has proposed using streaming architecture to provide a leap in media applications that are poorly matched to conventional processor architecture. Besides, low power considerations are becoming an important issue for mobile systems, but streaming architecture solutions do not fit in above requirements. Therefore, in this research, a combination of media streaming architecture and low power circuitry design methodology is proposed. An ALU Cluster design for media streaming architecture is presented in this thesis, which is based on Stanford Imagine stream architecture with the consideration of implementation feasibility. The back-end simulation results decide the final micro-architecture of each component, and utilize communication bandwidth hierarchy design to effectively solve the problem of scarce memory bandwidth. The experimental results show that the power and energy consumption of selected benchmark for multimedia and baseband communication systems become scalable by dynamic selecting the number of utilized ALU Clusters. Thus, the instant performance and energy consumption of an entire work can be optimized for mobile systems. The proposed design has provided a breakthrough for similar architectures.
摘要................................................................................................................................I

Abstract........................................................................................................................II

Acknowledgments......................................................................................................III

Chapter 1 Introduction................................................................................................1

Chapter 2 Background.................................................................................................4
2.1 Design Methodology........................................................................................4
2.2 Stream Processing Model.................................................................................9
2.3 Related Research............................................................................................11
2.4 Low Power Considerations............................................................................13
2.5 Media Streaming Processor Architecture.......................................................13

Chapter 3 Design of ALU Cluster Microarchitecture.............................................16
3.1 ALU Cluster Block Diagram..........................................................................16
3.2 Instruction Set Format....................................................................................18
3.3 ALU Cluster Function Units...........................................................................19
3.3.1 ALU Unit.............................................................................................20
3.3.2 MUL Unit............................................................................................21
3.3.3 DIV Unit..............................................................................................22
3.3.4 IRF Unit...............................................................................................23
3.3.5 SPRF Unit............................................................................................24
3.3.6 Decoder Unit.......................................................................................25
3.3.7 Controller Unit....................................................................................25
3.4 System Operation...........................................................................................25

Chapter 4 Implementation.........................................................................................28
4.1 Design Flow....................................................................................................28
4.2 Circuit Implementation and Results...............................................................31
4.3 Circuit Verification and Performance Evaluation….......................................35
4.3.1 Test Bench: FIR Filter.........................................................................35
4.3.2 Functionality Verification....................................................................37
4.3.3 Performance Evaluation Results.........................................................41
4.4 Performance Comparison...............................................................................44
4.5 Low Power Techniques Implementation........................................................45
4.6 Summary.........................................................................................................49

Chapter 5 Conclusion.................................................................................................51

Bibliography................................................................................................................52

Appendix A: Summary of the Defined Microcode in Instruction Set....................55
Appendix B: Assemby Code of Test Bench................57
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