臺灣博碩士論文加值系統

在現今多媒體應用上，影像處理、視訊壓縮、二維和三維繪圖、資料複製和資料搬移是常見的程序。然而，處理器和記憶體之間的頻寬差距造成傳輸資料減速。為了縮短現今多媒體影像處理架構上的差距，這篇論文提出了一個分散式記憶體管理單元。分散式記憶體管理單元包含位址轉換單元和雙倍資料率記憶體控制器。位址轉換單元提供一個虛擬記憶體機制和用來節省資料傳輸時間。雙倍資料率記憶體控制器用於簡易地爆發讀取和寫入模式。從分散式記憶體管理單元實現的結果顯示，當傳送十六百萬位元組資料量時，提出的位址轉換單元架構比傳統的位址轉換單元速度提升了二百萬倍。然而，當資料量小於十六百萬位元組時，無位址轉換單元傳輸時間與有位址轉換單元傳輸時間相比會隨著資料量的增加而增加。本篇論文便是針對現今多媒體應用架構中，用微量增加的電路面積和功率消耗以換取資料傳輸效能的躍進。

In modern multimedia applications such as image processing, video compression, two-dimension and three-dimension graphics, data copying and data moving are common processes. However, the bandwidth gaps between processors and memory cause the slow down of transition data. In order to bridge the gap, this thesis proposed a distributed memory management unit (DMMU) for modern media processing architectures. The DMMU consists of address translation unit (ATU) and double data rate (DDR) memory controller. The ATU provides a virtual memory mechanism, and been used to save data transition time. The DDR memory controller is used in simply burst read and burst write mode. The result of DMMU implementation shows that proposed ATU architecture provides 2 million times speed-up than conventional ATU when transmitted 16MB data size. However, when the data capacity is less than 16MB, the proportion of the transition time without ATU/ ATU is increased for the data capacity. The proposed design provides a leap up in data transition for modern media processing architecture with a tiny overhead in circuit area and power.

Contents
中文摘要......I
English Abstract......II
Acknowledgments......III
Content......IV
List of Tables......V
List of Figures......VI
Chapter1 Introduction......1
1.1 Motivation......1
1.2 Organization......4
Chapter2 DMMU Design Architecture......5
2.1 Data Copying and Data Moving in Address Translation Unit......5
2.2 Distributed Memory Management Unit......7
2.3 Address Translation Unit......9
2.4 DDR Memory Controller......12
2.4.1 Device Operations of DDR SDRAM......12
2.4.2 Mode Register Definition of DDR SDRAM......15
2.4.3 Block Diagram of DDR Memory Controller......16
2.4.4 The Main Controller Module......17
2.4.5 Summary......19
Chapter3 Implementation......20
3.1 Computer-Aided Design Flow......20
3.2 Implementation of DMMU Interface......23
3.3 Circuit Verification......25
3.4 Functional Verification......29
3.5 Performance Evaluation......45
3.5.1 Comparison......45
3.6 Summary......49
Chapter4 Conclusions......51
Bibliography......52

List of Tables
Table 2.1 The supervisor and users access privileges and correspond to PR bits.....12
Table 3.1 The signals on the DMMU interface.....24
Table 3.2 The results of the ATU synthesis.....26
Table 3.3 The results of the DMMU synthesis.....26
Table 3.4 The results of the P&R in core utilization = 0.7.....27
Table 3.5 The results of the P&R in core utilization = 0.8.....27
Table 3.6 The core area of the P&R results between the different core utilization and clock frequency.....27
Table 3.7 The specification table of the design.....28
Table 3.8 The different parameter values during initial states.....30
Table 3.9 The different parameter values during command states.....30
Table 3.10 The test bench of the ATU.....33
Table 3.11 The clock period of the micro-controller, the DMMU and DDR.....46
Table 3.12 The data transition time of data copying and data moving in the different data capacity without ATU.....46
Table 3.13 Total access time of two ATU modes.....48

List of Figures
Figure 1.1 The performance gap of CPU and memory.....1
Figure 1.2 Bandwidth hierarchy of an imagine stream architecture.....2
Figure 1.3 Time to complete a series of memory references without access scheduling.....3
Figure 1.4 Time to complete a series of memory references with access scheduling.....3
Figure 1.5 Memory access scheduler architecture.....3
Figure 2.1 The page table of traditional address translation.....6
Figure 2.2 The proposed ATU mechanism in the DMMU.....6
Figure 2.3 The proposed DMMU micro-architecture in the streaming memory system of the imagine stream processor.....8
Figure 2.4 The proposed memory system.....8
Figure 2.5 The block diagrams of the DMMU micro-architecture.....9
Figure 2.6 The flows of the address translation.....9
Figure 2.7 The stream register file organization.....10
Figure 2.8 The translation table of the address translation mode.....11
Figure 2.9 The block diagram of DDR SDRAM 512Mb B-die.....13
Figure 2.10 The simplified state diagram of the DDR SDRAM.....15
Figure 2.11 The mode register set of DDR SDRAM.....16
Figure 2.12 The functional block diagram of the DDR memory controller.....17
Figure 2.13 Initial state diagram of DDR memory controller.....18
Figure 2.12 The command state diagram of DDR memory controller.....19
Figure 3.1 The cell-base design flow.....21
Figure 3.2 The physical level design flow.....22
Figure 3.3 The DMMU interface.....23
Figure 3.4 Layout of DMMU.....28
Figure 3.5 The operation environment of DMMU functional verification.....29
Figure 3.6 The initial state machine of DDR memory controller.....31
Figure 3.7 The burst write and burst read mode of DDR memory controller.....32
Figure 3.8 Access data (PR = 2’b00) under supervisor mode in the DMMU.....35
Figure 3.9 Access data (PR = 2’b01) under supervisor mode in the DMMU.....36
Figure 3.10 Access data (PR = 2’b10) under supervisor mode in the DMMU.....37
Figure 3.11 Access data (PR = 2’b11) under supervisor mode in the DMMU.....38
Figure 3.12 Access data (PR = 2’b00) under users mode in the DMMU.....40
Figure 3.13 Access data (PR = 2’b01) under users mode in the DMMU.....41
Figure 3.14 Access data (PR = 2’b10) under users mode in the DMMU.....42
Figure 3.15 Access data (PR = 2’b11) under users mode in the DMMU.....43
Figure 3.16 Data capacity over limitation in the DMMU.....44
Figure 3.17 Test configuration environment.....45
Figure 3.18 The access time versus the data capacity for different ATU.....48
Figure 3.19 The proportion of the access time without ATU/ATU versus the different data capacity.....49

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