參考文獻
[1] Maxim, A., “A 2-5GHz low jitter 0.13um CMOS PLL using a dynamic current matching charge-pump and a noise attenuating loop-filter,” Custom Integrated Circuits Conference, 2004. Proceedings of the IEEE 2004 3-6 Oct. 2004 Page(s):147-150
[2] K. Taura, et al., “A Digital Audio Broadcasting (DAB) Receiver,” IEEE Transactions on Consumer Electronics, Vol.42, No, 3, pp. 322-327, August 1996.
[3] 王仲宗,數位音訊廣播接收機 L 頻帶降頻器及相關單晶射頻微波積體電路之研製, 國立成功大學電機工程學研究所碩士論文,民國八十七年。[4] Yoshizawa,H.; Taniguchi,K.; Nakashi,K., “An implementation technique of dynamic CMOS circuit applicable to asynchronous/synchronous logic,” Circuits and Systems, 1998.ISCAS‘98.Proceedings of the 1998 IEEE International Symposium on Volume 2, 31 May-3 June 1998 Page(s):145-148vol. 2
[5] Arshak, K; Abubaker, O; Jafer, E, “Design and simulation difference types CMOS phase frequency detector for high speed and low jitter PLL,” Devices,Circuits and Systems, 2004. Proceedings of the Fifth IEEE International Caracas Conference on Volume 1, 3-5 Nov. 2004 Page(s):188-191
[6] Kuo-Hsing Cheng; Tse-Hua Yao; Shu-Yu Jiang; Wei-Bin Yang, “A difference detector PFD for low jitter PLL,”Electronics, Circuits and Systems,2001.ICECS 2001. The 8th IEEE International Conference on Volume 1, 2-5 Sept 2001 Page(s):43-46 vol.1.
[7] Johnson,T.; Fard,A.; Aberg,D., “An improved low voltage phase-frequency detector with extended frequency capability,”Circuits and Systems, 2004. MWSCAS 2004, The 2004 47th Midwest Symposium on Volume 1, 25-28 July 2004 Page(s):1-181-4 vol.1.
[8] Maxim,A, “A 2-5GHz low jitter 0.13/spl mu/m CMOS PLL using a dynamic current matching charge-pump and a noise attenuating loop-filter,”Custom Integrated Circuits Conference,2004. Proceedings of the IEEE 2004 3-6 Oct. 2004 Page(s):147-150
[9] Chung-Yu Wu; Chih-Yuan Hsieh; Wei-Ming Chen, “A 1-V 2.4GHz CMOS frequency synthesizer with current-match charge pump,” Circuits and Systems, 2004. Proceedings. The 2004 IEEE Asia-Pacific Conference on Volume 1, 6-9 Dec. 2004 Page(s):433-436 vol. 1
[10] Kuo-Hsing Cheng;Tse-Hua Yao;Shu-Yu Jiang;Wei-Bin Yang,“A difference detector PFD for low jitter PLL,”Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on Volume 1, 2-5 Sept. 2001 Page(s):43-46 vol.1
[11] Geum-Young Task; Seok-Bong Hyun; Tae Youny Kang; Byoung Gun Choi; Seong Su Park, “A 6.3-9GHz CMOS fast settling PLL for MB-OFDM UWB applications,” Solid-state Circuits, IEEE Journal of Volume 40, Issue 8, Aug. 2005 Page(s):1671-1679
[12] Chien-Ping Chou; Zhi-Ming Lin; Jun-Da Chen, “A double-edge-checking phase-frequency-detector with 4.78GHz operating frquencies,” Circuits and Systems,2004.Proceedings. The 2004 IEEE Asia-Pacific Conference on Volume 2, 6-9 Dec. 20004 Page(s):937-940 vol.2
[13] Johnson, T.; Fard, A.; Aber, D,“An Improved Low Voltage Phase-Frequency Detector with Extended Frequency Capability,”Circuits and Systems, 2004. MWSCAS ‘04 .The 2004 47th Midwest Symposium on Volume 1, 25-28 July 2004 Page(s): 1-181-4 vol.1
[14] 王嘉仁,應用於數位電視寬頻調諧器及數位音訊廣播接收機之CMOS頻率合成器的設計研究, 國立成功大學電機工程學研究所碩士論文,民國九十二年。[15] 吳重雨, 類比積體電路(一), 交通大學, 台灣, 2003
[16] Te-Hsien Hsu,“A Low Spurious Tones of 5-GHz CMOS Frequency Synthesizer with New Current-Match Charge Pump, ” National Chiao Tung University, 2004.
[17] W.-H. Lee, J.-D. Cho, S.-D. Lee,“A High Speed and Low Power Phase-Frequency Detector and Charge-pump,”Design Automation Conference, 1999 Proceedings of the ASP-DAC ‘99 .Asia and South Pacific, vol.1,pp.269-272,1999.
[18] Behzad Razavi,“Design of Analog CMOS Integrated Circuits, ” McGraw-Hill, 2001.
[19] Houng-Liang Pan, “Design of CMOS RF Synthesizer for 802.11a,” National Chiao Tung University, 2003.