臺灣博碩士論文加值系統

本論文中主要提出一個應用於之全積體化低功率快速鎖定整數型頻率合成器，另外還有一個寬頻壓控震盪器與其除頻電路，這兩個電路都是應用於多頻帶正交分頻多工超寬頻系統。
首先，利用台積電0.18微米互補式金氧半導體製程來實現一個寬頻壓控震盪器和其除頻電路，可以產生多頻帶正交分頻多工超寬頻系統的第一、第三和第四個頻帶群所需要的八個載波頻率。量測結果如下：可調頻寬為6122∼9149兆赫茲（壓控震盪器產生）與3061∼3930兆赫茲（除頻電路產生），在距離一兆赫茲處的相位雜訊為-105.5∼-115.1分貝/赫茲，總功率消耗為36.63毫瓦。
接下來也是利用台積電0.18微米互補式金氧半導體製程來實現一個低功率快速鎖定整數型頻率合成器，產生多頻帶正交分頻多工超寬頻系統的第三和第四個頻帶群所需要的六個載波頻率。其模擬結果如下：可調頻寬為6279∼9170兆赫茲，在距離一兆赫茲處的相位雜訊為-109.8∼-113.6分貝/赫茲，寄生雜頻較主頻低-34.2∼-55.5分貝，鎖定時間小於0.3微秒，正交相位誤差為3.1度，總功率消耗為46.35毫瓦。

In this thesis, a low power and fast-locking integer-N frequency synthesizer is introduced. Additionally, a wideband voltage-controlled oscillator (VCO) and its frequency divider are designed. These two circuits are both suitable for MB-OFDM UWB application.
First, the wideband VCO and its frequency divider are demonstrated. They are fabricated in TSMC 0.18 μm CMOS process. They can generate eight carrier frequencies in Band Group #1, #3, and #4. The measurement shows that the tuning range is 6122~9149 MHz from the VCO and 3061~3930 MHz from the divider. Moreover, the phase noise is -105.5~-115.1 dBc/Hz at 1 MHz offset and the total power dissipation is 36.63 mW.
Besides, the low power and fast-locking integer-N frequency synthesizer using TSMC 0.18 μm CMOS process is also described. It provides six carrier frequencies in Band Group #3 and #4. The simulated results are listed: the tuning range is 6279~9170 MHz, the phase noise is -109.8~-113.6 dBc/Hz at 1 MHz offset, the spurious tone is -34.2~-55.5 dBc, the locking time is less than 3 nsec, the I/Q phase mismatch is 3.1°, and total power dissipation is 46.35 mW.

Chinese Abstract...........................................I
English Abstract..........................................II
Acknowledgement..........................................III
Contents..................................................IV
List of Tables............................................VI
List of Figures..........................................VII

Chapter 1 Introduction.....................................1
1.1 Background and Motivation..............................1
1.2 Specification of the Frequency Synthesizer.............4
1.3 Thesis Organization....................................6

Chapter 2 Wideband Voltage-Controlled Oscillator and Its Frequency Divider for MB-OFDM UWB system...................8
2.1 Circuit Design Consideration...........................8
2.1.1 Multi-Band Voltage-Controlled Oscillator.............9
2.1.2 High Frequency Divider..............................15
2.1.3 2-to-1 Multiplexer..................................19
2.2 Chip Layout and Simulation Results....................20
2.3 Measurement Results...................................34
2.4 Summary and Comparison................................41

Chapter 3 Low Power and Fast-Locking Integer-N Frequency Synthesizer for MB-OFDM UWB System........................43
3.1 Architecture..........................................43
3.2 Circuit Design Consideration..........................45
3.2.1 Quadrature Voltage-Controlled Oscillator............48
3.2.2 Multi-Modulus Divider...............................51
3.2.3 Fast Phase-Frequency Detector.......................54
3.2.4 Charge Pump.........................................58
3.2.5 Loop Filter.........................................59
3.2.6 Wideband Output Buffer..............................62
3.3 Chip Layout and Simulation Results....................64
3.3.1 Behavior Simulation.................................65
3.3.2 Circuit Simulation..................................68
3.4 Summary and Comparison................................77

Chapter 4 Conclusions and Future Work.....................80
4.1 Conclusions...........................................80
4.2 Future Works..........................................81

Reference.................................................83

Publishing Remarks........................................87

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