臺灣博碩士論文加值系統

隨著製程技術的進步，超大型積體電路系統可以用更小的晶片面積達到更高的運算速度。在現行的通訊系統中，訊號將先透過一個類比數位轉換器將接收到的類比訊號量化，以供後級的數位電路執行更複雜的訊號處理；為提昇整體系統之性能，類比數位轉換器往往和龐大的數位訊號處理系統整合在單一顆晶片上。 伴隨著電晶體尺寸的縮小，系統晶片的供應電壓也隨之下降。因此，低電壓類比數位轉換器將伴演愈形重要的角色。

本論文中的主要目標為設計一個操作在1.8V DC之下、10位元、每秒200百萬次取樣導管式類比數位轉換器。其採用每級1.5-bit解析度的架構，以提高整體類比數位轉換器的運算速度。同時結合數位校正技術以增加比較器的偏移電壓容忍度，而不須要前級預先放大器，進而節省功率的耗費。為了因應低電源電壓的操作，本設計利用升壓技術(bootstrapping technique)以控制取樣開關，進而減低因低電壓操作時對取樣保持電路線性度的影響。

整個類比數位轉換器原型晶片以TSMC 0.18μm CMOS製程製作，晶片面積為3.2mm2；當輸入為1.6Vpp的差動訊號且在200MHz的轉換速度(conversion rate)之下，此類比數位轉換器達到65dB訊號雜訊動態範圍(SNDR)，微分型非線性誤差(DNL)和積分型非線性誤差(INL)小於0.2LSB, 0.2LSB，其電源供應為1.8V的單電
壓，功率消耗為150mW。

Acknowledgements IX
List of Tables XII
List of Figures XIII

CHAPTER 1. INTRODUCTION
1.1 MOTIVATION 1
1.2 THESIS ORGANIZATION 1

CHAPTER 2. PIPELINE ADC OVERVIEW
2.1 INTRODUCTION 3
2.2 PIPELINE A/D CONVERTERS 3
2.2.1 SINGLE BIT v.s. MULTI BIT 6
2.2.2 PIPELINE ADC DESIGN STRATEGY 7
2.2.3 DIGITAL ERROR CORRECTION 10
2.3 DYNAMIC AND STATIC PERFORMANCE 11
2.4 COHERENT SAMPLES 20
2.5 HISTOGRAM TESTING DETERMINES DNL 22
AND INL ERRORS CODE DENSITY
2.6 MATLAB BEHAVIOR MODEL 25

CHAPTER 3. A/D CONVERTER CIRCUIT DESIGN I
3.1 INTRODUCTION 28
3.2 CIRCUIT SPECIFICATIONS 28
3.3 CIRCUIT DESIGN 29
3.3.1 FIRST STAGE OF MDAC 29
3.3.2 BOOTSTRAPPED SWITCH 31
3.3.3 OPERATION AMPLIFIER 32
3.3.4 COMPARATOR 36

CHAPTER 4. A/D CONVERTER CIRCUIT DESIGN II
4.1 CLOCK GENERATER 38
4.2 BIASED CIRCUIT 40
4.3 FULL DIGITAL CORRECTION 43
4.4 OPTIMIZATION 44
4.5 CALIBRATION 46
4.6 SAMPLING-TIME UNCERTAINTY (APERTURE
JITTER) 48
4.7 SYSTEM SIMULATION AND PIN ASSIGNMENT 49

CHAPTER 5. TESTING SETUP AND EXPERIMENTAL
RESULT
5.1 SERIAL BUS 55
5.2 TESTING BOARD CONSIDERATIONS AND
ENVIRONMENTS 56
5.3 EXPERIMENTAL RESULTS 62

CHAPTER 6. CONCLUSIONS AND FUTURE WORK
6.1 CONCLUSIONS 67
6.2 FUTURE WORK 67

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