跳到主要內容

臺灣博碩士論文加值系統

(44.192.15.251) 您好!臺灣時間:2024/02/25 07:30
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

: 
twitterline
研究生:黃世宗
研究生(外文):Shih-Tsung Huang
論文名稱:減少電壓壓降產生與藕合電容的再繞線方法論
論文名稱(外文):Voltage Drop Repair and Coupling Capacitance Reduction during ECO
指導教授:陳宏明陳宏明引用關係
指導教授(外文):Hung-Ming Chen
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電機學院碩士在職專班電子與光電組
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2006
畢業學年度:94
語文別:中文
論文頁數:39
中文關鍵詞:電壓藕合電容繞線
外文關鍵詞:ECOvoltage dropcoupling capacitance
相關次數:
  • 被引用被引用:0
  • 點閱點閱:268
  • 評分評分:
  • 下載下載:13
  • 收藏至我的研究室書目清單書目收藏:0
本論文研究之重點在APR的ECO可能遇上IR Drop和 coupling capacitance的問題,在此提出一種方法可以在做完ECO仍然有機會去修復這些問題.在此, 提供一個方法可以利用lower metal layers 以及在很短的時間 就可以在 ECO 的階段局部有效改善 IR drop 和 coupling capacitance 的問題
ECO could suffers voltage drop and coupling capacitance issues.We formulate this problem as a longest path problem and fix the violation by using lower metal layer power lines.
1 Introduction 1
1.1 Previous Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 Our Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 ECO (Engineering Change Order) 5
2.1 ECO Basic Understandings . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Traditional ECO Flows . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3 Freeze ECO Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 ECO Flow using Physical Compiler . . . . . . . . . . . . . . . . . . . 8
3 Preliminaries 10
3.1 Previous Works on ECO . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1.1 On-chip Bus ECO Optimization . . . . . . . . . . . . . . . . . 10
3.1.2 Removing Overlaps between Power and Signals . . . . . . . . 11
3.1.3 Removing Overlaps for Coupling Capacitance Reduction during
ECO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2 Problem Formulation . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
iii
4 Our Methodology for Voltage Drop Repair and Coupling Capacitance
Reduction 16
4.1 Voltage Drop Estimation with Astro . . . . . . . . . . . . . . . . . . 17
4.2 Spot the Severe IR Drop Region . . . . . . . . . . . . . . . . . . . . . 18
4.3 Voltage Drop Compensation . . . . . . . . . . . . . . . . . . . . . . . 19
4.3.1 Graph-related Data Preparation . . . . . . . . . . . . . . . . . 21
4.3.2 Find the Longest Path for Power Compensation . . . . . . . . 22
4.3.3 Rip Up the Disturb Nets and Route Power Net for Compensation 24
4.3.4 Re-route these Disconnected Nets . . . . . . . . . . . . . . . . 24
4.4 Power Analysis and Noise Analysis after Compensation . . . . . . . . 26
5 Experimental Results 27
5.1 Power Analysis and Noise Analysis in Astro . . . . . . . . . . . . . . 28
5.1.1 Power Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.1.2 Noise Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.2 Voltage Drop Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.3 Coupling Capacitance Result . . . . . . . . . . . . . . . . . . . . . . . 30
5.4 Voltage Drop and Crosstalk Results with Different Voltage . . . . . . 31
6 Conclusions and Future Works 37
[1] Hung-Ming Chen; Li-Da Huang; I-Min Liu; and Martin D.F. Wong,” Simultaneous power supply planning and noise avoidance in floorplan design,iccad,24:578-587, 2005
[2]Murat Becer; Ravi Vaidyanathan; et al. ,”Signal Integrity Management and SoC Physical Design Flow”, ISPD’03
[3] Hua Xiang, et al., ”An ECO Routing algorithm for Eliminating Coupling Capacitance Violation”, IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems, 2005
[4] Hua Xiang; Kai-Yuan; Wong, D.F “ECO algorithm for removing overlaps between power rails and signal wires”, ICCAD 2002
[5]Singh,J;Sapatnekar, S.s, “Congestion-aware topology optimization of structure power/ground networks “,TCAD,24:683-695,2005
[6] Niv Margalit ,”ECO Flow – Using Physical Compiler”,Cisco System Israel, SNUG 2004
[7] Deng L; Wong, M.D.F ,”Optimal algorithm for minimizing the number of twists in an on-chip bus”,DATE 2004
[8] “Astro User Guide”
[9] “Laker PnR editor”,2005
[10]G Bai; S Bobba Hajj; I.N,”Power bus maximum voltage drop in digital VLSI circuits”, ISQED, page 263-268, Mar. 2000
[11]Jun Cheng Chi; Tsung Hui Huang; Mely Chen Chi, “An IR drop-driven placer for standard cells in a SOC design”, 2:29-32, Sept. 2005
[12]J Cong; Jie Fang; Kei-Yong Khoo, “An implicit connection graph maze routing algorithm for ECO routing”,iccad,163-167, Nov. 1999
[13]Xiaopeng Dong; inhwan Seo; W Kao, “New metal fill considerations for nanometer technologies”, ASICON 2:802-805,Oct. 2005
[14]Wnag Donghui; Yu Qian; Hong Ying; Hou Chanhuan, “SuperV back-end design flow based on Astro”, ieee, 2:1524-1527, Oct. 2005
[15]Xiang Hua; et al., “An ECO algorithm for resolving OPC and coupling capacitance violations”, ASICON, Oct. 2005
[16]Xiang Hua; et al., “An ECO Algorithm for Eliminating Crosstalk Violations”, ISPD, 24:683-695, May 2005
[17]Niv Margalit, “ECO-Flow – Using Physical Compiler”, volume 1, 2004
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top