臺灣博碩士論文加值系統

在此篇論文中，我們提出了一個具有可變係數的AES (Configurable AES)加解密器，使得在不同的m(x)、c(x) 和affine transformation係數選擇之下，可產生多變的AES演算法，藉以進一步的提高系統的安全性。並由於我們所提出之硬體實現仍能具有高效能的表現，讓此構想可以跟到上網路傳輸速度的進步，運到用Gigabit的光纖與乙太網路安全晶片上。在規格上，除了可調變係數之外，並支援128, 192, 256-bit三種金鑰長度以及ECB, CBC兩種加密模式。對於加解密過程中所需之金鑰，我們也提出了一種可同步計算金鑰的電路，而不需使用額外的記憶體來儲存金鑰。此外，為了降低硬體成本和提升效率，我們採取Composite Field Arithmetic運算來實現演算法的核心S-Box部分，並將架構下的矩陣乘法運算合而為一以縮短運算時間。最後，以強調重複利用的矽智產方式 (IP-based)實現，並遵守AMBA AHB Slave傳輸協定，以助於未來在系統面的開發。在本論文的成果方面，此Configurable-AES加解密器以UMC 0.18μm CMOS製程實現，擁有約81K的gate counts，在最高處理速度下，對於128/192/256三種不同金鑰長度下，分別可達到3.2Gbps、2.67 Gbps和2.29 Gbps。

In this paper, we implement a configurable AES (C-AES) coprocessor, which supports all specified key lengths, such as 128, 192, and 256 bits, and both the ECB and CBC operation modes. The round keys for encryption and decryption are generated on the fly without any internal memory. Specifically, it provides the flexibility to change the parameters of each transformations, such as the irreducible polynomial, the affine matrix, the affine constant, and the row vector of the matrix used in MixColumns(). These parameters are online changeable, i.e., they are also the inputs of the circuit. For increasing the speed, an optimized combination is presented in the proposed architecture. By using basis conversion and composite field in SubBytes(), and pre-calculating the values of every power of xtime() of constants in MixColumns(), the matrix multiplications in SubBytes() and MixColumns() can be integrated into a new transformation to reduce the computation path. Furthermore, all arithmetic components are also reused for the encryption and the decryption data paths. The proposed design has been implemented using a UMC 0.18μm CMOS technology. The throughput is about 3.2Gbps for 128-bit keys, 2.67Gbps for 192-bit keys, and 2.29Gbps for 256-bit keys, respectively. The total gate count is about 81K. This work provides a customized AES cipher to let users change parameters; therefore, it can be utilized in the applications requiring customized security, .e.g., the virtual private networks (VPN).

Chapter 1 Introduction ..........................................................................1
1.1 Background......................................................................................................1
1.2 Motivation........................................................................................................2
1.3 Organization.....................................................................................................3
Chapter 2 AES Algorithm .....................................................................4
Chapter 3 Hardware-Reduction Strategy for C-AES.......................10
3.1 Previous Work................................................................................................10
3.2 S-Box Optimization .......................................................................................11
3.2.1 Composite Field Arithmetic................................................................12
3.2.2 Isomorphism Functions and Basis Transformation.............................13
3.2.2 Multiplicative Inversion over the Composite Field ............................15
3.2.3 The Comparison of Multiplicative Inversion......................................18
3.3 MixColumns() Optimization ..........................................................................20
3.4 The Hardware Architecture............................................................................21
3.4.1 The Direct Architecture.......................................................................22
3.4.2 The Combination of SubBytes() and MixColumns()...........................23
Chapter 4 3-in-1 Key Expansion Design ............................................28
4.1 The Data Flow Graph of Key Expansion.......................................................28
4.1.1 128-bit Key Expansion .......................................................................29
4.1.2 192-bit Key Expansion .......................................................................29
4.1.2 256-bit Key Expansion .......................................................................31
4.2 The Hardware Architecture of 3-in-1 Key Generator ....................................33
Chapter 5 The Implementation of C-AES coprocessor.......................37
5.1 Top-level View...............................................................................................37
5.2 I/O Interface ...................................................................................................39
5.2.1 Input Interface.....................................................................................39
5.2.2 Output Interface ..................................................................................41
5.3 Parameter initialization Engine......................................................................41
Chapter 6 Verification and Result Comparison...................................43
6.1 IP-Based Design.............................................................................................43
6.1.1 IP Qualification Guideline Overview .................................................43
6.1.2 Soft IP Design Flow............................................................................44
6.2 Chip Design Flow ..........................................................................................46
6.3 Verification Strategy ......................................................................................48
6.3.1 Untimed functional model ..................................................................48
6.3.2 Timing Accurate model.......................................................................48
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6.3.3 FPGA Prototyping...............................................................................49
6.3.4 Coding Style Rule Check....................................................................51
6.3.5 Code Coverage....................................................................................51
6.3.6 Design for Testability..........................................................................52
6.3.7 Physical Verification ...........................................................................53
6.4 Results and Comparisons...............................................................................53
Chapter 7 Conclusions and Future Work.............................................57
7.1 Conclusions....................................................................................................57
7.1 Future Work ...................................................................................................57

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