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研究生:余俊德
研究生(外文):Jiunn-Der Yu
論文名稱:內嵌式記憶體中位址及資料匯流排之串音瑕疵測試
論文名稱(外文):Testing Crosstalk Faults of Address and Data Buses in Embedded Memories
指導教授:李進福李進福引用關係
指導教授(外文):Jin-Fu Li
學位類別:碩士
校院名稱:國立中央大學
系所名稱:電機工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2006
畢業學年度:94
語文別:英文
論文頁數:64
中文關鍵詞:內嵌式記憶體串音瑕疵測試
外文關鍵詞:embedded memoriescrosstalk faultstesting
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隨著互補式金屬氧化物半導體 (CMOS) 製程尺寸的下降,串音缺陷 (crosstalk defect) 已經成為積體電路故障的重要因素。因此,現今的積體電路測試必須考量串音瑕疵 (crosstalk fault)。這篇論文針對了單埠 (single-port) 及多埠 (multiple-port) 記憶體中位址及資料匯流排之最大侵略串音瑕疵 (maximal aggressor crosstalk faults) 提出了兩個測試演算法。就擁有m位元位址及n位元資料輸入/輸出匯流排之單埠 (single-port) 及多埠 (multiple-port) 記憶體而言,其測試演算法分別需要2m+6n+2及4m+12n+8個執行動作來涵蓋100%的串音瑕疵。此外,這篇論文更提出一用於單埠記憶體且可同時提供串音瑕疵測試及March-CW測試的內建自我測試電路 (BIST) 架構。使用TSMC 0.18um standard cell technology合成實現內建自我測試電路 (BIST),就一個8k×32位元的單埠記憶體而言,此內建自我測試電路 (BIST) 設計需要額外支出的面積大約是2%,且其延遲時間大約是2.1ns。
With the scaling of CMOS technology, the crosstalk defect has become an important cause of failure in integrated circuit (IC) designs. Therefore, crosstalk faults must be considered in modern IC testing. This thesis presents two test algorithms for maximal aggressor crosstalk faults on address and data buses of single-port and multiple-port memories. The two test algorithms require 2m+6n+2 and 4m+12n+8 operations to cover 100% crosstalk faults for a single-port and multiple-port memories with m-bit addresses and n-bit data I/Os. A BIST scheme which can support the test algorithms for crosstalk faults and March-CW [1] test for single-port RAMs is also proposed. Experimental results show that the area overhead of the BIST design for an 8k×32-bit single-port memory is about 2%. The delay of the BIST synthesized with TSMC 0.18um standard cell technology is about 2.1ns.
Chapter 1 Introduction (1)
Chapter 2 Preliminary (3)
2.1 Overview of Random Access Memories (3)
2.2 Targeted Crosstalk Faults in Address and Data Buses (5)
2.3 Sufficient and Necessary Conditions for Detecting XFs (7)
2.4 Crosstalk-Fault-Detection Ability of March Tests (11)
Chapter 3 Test Algorithms for Address and Data Buses XFs in Single-Port and Multiple-Port RAMs (12)
3.1 Proposed Test Algorithms for Single-Port Memories (12)
3.2 Proposed Test Algorithms for Multiple-Port Memories (27)
3.2.1 A Test for Multiple-Port Memories (29)
3.3 Complexities of Proposed Algorithms (39)
Chapter 4 BIST Design (43)
4.1 BIST Architecture (43)
4.2 BIST Implementation (45)
4.3 Experimental Results (50)
Chapter 5 Conclusions (53)
Reference (54)
[1] Chi-Feng Wu, Chih-Tsun Huang, and Cheng-Wen Wu, “RAMSES: a fast memory fault simulator,” International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT 1999), Nov. 1999, pp. 165-173.

[2] The International Technology Roadmap for Semiconductors 2005 (2005 ITRS Roadmap), Semiconductor Industry Association (SIA), Apr. 18-20, 2005, http://public.itrs.net.

[3] M. Cuviello, S. Dey, X. Bai, and Y. Zhao, “Fault Modeling and Simulation for Crosstalk in System-on-Chip Interconnects,” IEEE/ACM International Conference on Computer-Aided Design (ICCAD1999), Nov. 1999, pp. 297-303.

[4] W.-C. Lai, J.-R. Huang, and K.-T. Cheng, “Embedded-Software-Based Approach to Testing Crosstalk-Induced Faults at On-Chip Buses,” in Proc. IEEE on VLSI Test Symposium (VTS2001), May 2001, pp. 204-209.

[5] M. Redeker, B. F. Cockburn, and D. G. Elliott, “An Investigation into Crosstalk Noise in DRAM Structures,” in Proc. IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002), July 2002, pp. 123-129.

[6] Ashok K. Sharma, Advanced Semiconductor Memories: Architectures, Designs, and Applications, Wiley-Interscience, Piscataway, NJ, 2003.

[7] K. Osada, Y. Saitoh, E. Ibe, and K. Ishibashi, “16.7 fA/cell Tunnel-Leakage-Suppressed 16 Mb SRAM for Handling Cosmic-Ray-Induced Multi-Errors,” IEEE International Solid-State Circuits Conference (ISSCC 2003) Digest of Technical Papers, Feb. 2003, pp. 302-494.

[8] Y. Watanabe, H. Wong, T. Kirihata, D. Kato, J. K. DeBrosse, and et al., “A 286 mm2 256 Mb DRAM with ×32 both-ends DQ,” IEEE Journal of Solid-State Circuits, Vol. 31, No. 4, April 1996, pp. 567-574.

[9] A. J. van de Goor, Testing Semiconductor Memories: Theory and Practice, John Wiley & Sons, Chichester, England, 1991.

[10] S. Hamdioui, and A. J. van de Goor, “Efficient Tests for Realistic Faults in Dual-Port SRAMs,” IEEE Transactions on Computers, May 2002, pp. 460-473.

[11] D.S. Suk and S.M. Reddy, "A March Test for Functional Faults in Semiconductors Random-Access Memories," IEEE Trans. on Computers, 1981, pp. 982-985.

[12] M. Sachdev, “Test and Testability Techniques for Open Defects in RAM Address Decoders,” in Proc. European Design and Test Conference, March 1996, pp. 428-434.

[13] R. Nair, "An Optimal Algorithm for Testing Stuck-at Faults Random Access Memories," IEEE trans. on Computers, Vol. C-28, No. 3, 1979, pp. 258-261.

[14] D.S. Suk and S.M. Reddy, "A March Test for Functional Faults in Semiconductors Random-Access Memories," IEEE Trans. on Computers, 1981, pp. 982-985.

[15] S. Hamdioui, A.J. van de Goor, "Experimental Analysis of Spot Defects in SRAMs: Realistic Fault Models and Tests," in Proc. Ninth IEEE Asian Test Symposium (ATS2000), 2000, pp. 131-138.

[16] S. Hamdioui, A. J. van de Goor, and M. Rodgers, “March SS: A Test for All Static Simple RAM Faults,” in Proc. IEEE International Workshop on Memory Technology, Design and Testing (MTDT 2002), July 2002, pp. 95-100.
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