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研究生:楊侑承
研究生(外文):Yu-Cheng Yang
論文名稱:類神經網路應用於高階電流模型之研究
論文名稱(外文):High-Level Current Macro Model usingNeural Network
指導教授:劉建男劉建男引用關係
指導教授(外文):Chien-Nan Jimmy Liu
學位類別:碩士
校院名稱:國立中央大學
系所名稱:電機工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2006
畢業學年度:94
語文別:中文
論文頁數:52
中文關鍵詞:高階電流模型類神經網路
外文關鍵詞:high level current modelneural network
相關次數:
  • 被引用被引用:2
  • 點閱點閱:228
  • 評分評分:
  • 下載下載:23
  • 收藏至我的研究室書目清單書目收藏:0
再現今這個單晶片(System on Chip)系統設計的時代,為了要縮短設計的時
間,以及增加單晶片的可靠度與效能,便希望能在設計的初期就能夠知道每一個
區塊的電流資訊,如此就能及早作功率的最佳化,也能儘早考慮到SSN
(simultaneous switch noise) 和IR-drop 這類雜訊的影響。此外對於電源線的設計
與佈局,也有很大的幫助。因此高階的電流模型在單晶片設計上便有舉足輕重的
地位,而且在使用上不需要知道內部電路的資訊,就可以很快速的得到電路區
塊的電流波形,也使得在應用上非常方便,對於IP 智慧財產權的保護,更是有
幫助。
因此本篇論文提出了一個利用類神經網路來建立的高階電流模型,並利用
HSPICE 做部分波形的模擬,再利用階級化的技巧來簡化電路中電流波形和輸入
輸出轉態情況的關係,並合併同一級的輸入輸出來降低類神經網路的複雜度,就
可以利用類神經網路學習不同的輸入向量與其相對應電流波形之間的關係,利用
論文中提出的方法流程,可以針對不同的CMOS 數位組合電路建構個別的電流
模型,且在模型建好之後,能夠同時對不同形狀的電流波形做估計,可說是非常
方便有效率。
Nowadays, the era of system on chip design, we hope to know about the current
information of the logic block for shorting the design cycle and improving the
reliability and performance of the chips. Therefore we can optimize the power and
consider about the noise influence, such like SSN, IR-Drop, as soon as possible. And
the current information also help for the design of power line and layout. So the high
level current model plays an important role of the system on chip design. We do not
need to know the detail information for drawing the current waveform of the logic
block. And the IP protection is the advantage of the high level model.
In this thesis, we propose a high level current model constructed by neural
network. We got parts of current waveforms by HSPICE simulation. And use the
levelize technique to simplify the relationship of waveform and the input output
transition status. Merge the same level input and output can reduce the complexity of
the neural network. Follow the flow which we proposed, the model will be
constructed. We can use this model to estimate current waveforms which have
different shapes. It is very convenient use and efficient computation.
1. 序論....................................................................1
1.1. 研究動機................................................................................................1
1.2. 論文組織................................................................................................4
2. 背景知識...........................................................5
2.1. 相關研究................................................................................................5
2.1.1. 最大瞬時電流的估計....................................................................5
2.1.2. 閘級階層估計電流和雜訊............................................................7
2.1.3. 高階電流模型................................................................................8
2.2. 類神經網路(Artificial Neural Network) ...............................................9
2.2.1. 背景..............................................................................................10
2.2.2. 生物神經元模型(Biological Neuron) .........................................10
2.2.3. 人工神經元模型(Artificial Neuron) ...........................................11
2.2.4. 倒傳遞網路(Backpropagation)....................................................12
2.2.5. 類神經網路的運作......................................................................16
2.2.6. 類神經網路的訓練......................................................................16
2.2.7. 訓練的演算法..............................................................................17
3. 高階電流模型.................................................18
3.1. 簡介......................................................................................................18
3.2. 整體電流模型建構流程概述..............................................................19
3.3. 階級化(Levelize) .................................................................................21
3.4. 模型訓練所需要的輸入......................................................................23
3.5. 建立類神經網路模型..........................................................................24
3.5.1. 模型建立流程..............................................................................24
3.5.1.1. 主要輸入(Primary Input)的編碼.........................................25
3.5.1.2. 合併同一級的輸出與輸入..................................................26
3.5.1.3. 考慮每一級輸出的扇出數(Fan-Out)..................................27
3.5.1.4. 考慮前一級的輸入..............................................................28
3.5.2. 訓練LILO 模型..........................................................................29
3.5.3. 訓練波形的模型..........................................................................30
3.6. 電流模型的應用..................................................................................31
3.7. 總結......................................................................................................32
4. 實驗結果.........................................................34
4.1. 實驗流程與波型比較..........................................................................34
4.2. 數據彙整..............................................................................................45
5. 結論..................................................................48
參考文獻..............................................................50
[1] Krstic, A.; Kwang-Ting Cheng, “Vector Generation For Maximum Instantaneous
Current Through Supply Lines For CMOS Circuits”, Design Automation
Conference, Proceedings of the 34th, pp.383 - 388, 1997
[2] Yi-Min Jiang; Krstic, A.; Kwang-Ting Cheng, ” Estimation for maximum
instantaneous current through supply lines for CMOS circuits”, Very Large Scale
Integration (VLSI) Systems, IEEE Transactions on Vol 8, Issue 1, pp.61 –
73,2000.
[3] A. Nabavi-Lishi and N. C. Rumin, “Inverter models of CMOS gates for supply
current and delay evaluation,” IEEE Trans. Computer-Aided Design, vol. 13, pp.
1271–1279, 1994.
[4] A. Chatzigeorgiou, S. Nikolaidis, and I. Tsoukalas, “A modeling technique for
CMOS gates.”, IEEE Trans., Computer-Aided Design, vol. 18, pp. 557–575, 1999.
[5] Hamoui, A.A.; Rumin, N.C., “An analytical model for current, delay, and power
analysis of submicron CMOS logic circuits”, Circuits and Systems II: Analog and
Digital Signal Processing, IEEE Transactions, vol. 47, Issue 10, pp.999 – 1007,
2000.
[6] Boliolo, A.; Benini, L.; de Micheli, G.; Ricco, B. “Gate-Level Power and Current
Simulation of CMOS Integrated Circuits “, Very Large Scale Integration (VLSI)
Systems, IEEE Transactions , vol. 5 , Issue: 4 , 1997
[7] Zhao, S.; Roy, K.; Koh, C.-K, ”Estimation of inductive and resistive switching
noise on power supply network in deep sub-micron CMOS circuits”, Computer
Design, Proceedings, International Conference on17-20 Sept. pp:65 – 72,2000.
[8] Gupta, S.; Najm, F.N., “Analytical model for high level power modeling of
combinational and sequential circuits”, Low-Power Design. IEEE Alessandro
Volta Memorial Workshop, pp.164 – 172,1999.
[9] Bernacchia, G.; Papaefthymiou, M.C , ”Analytical macromodeling for high-level
power estimation.”, Computer-Aided Design, Digest of Technical Papers. 1999
IEEE/ACM International Conference on 7-11 Nov. pp.280 – 283,1999.
[10] Bodapati, S.; Najm, F.N,” Frequency-domain supply current macro-model.”,
Low Power Electronics and Design, International Symposium.pp.295 – 298, 2001.
[11] Bodapati, S.; Najm, F.N,” High-level current macro-model for power-grid
analysis.”, Design Automation Conference, pp.385 – 390,2002.
[12] Bodapati, S.; Najm, F.N.;” High-Level current macro model for logic blocks”,
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Vol. 25, Issue 5, pp.837 – 855,2006.
[13] Lipeng Cao, ”Circuit power estimation using pattern recognition techniques”,
Computer Aided Design, ICCAD.IEEE/ACM International Conference. pp.412 –
417,2002.
[14] Chih-Yang Hsu, Chien-Nan Jimmy Liu, and Jing-Yang Jou, “Efficient Vector
Compaction Methods for Power Estimation with Consecutive Sampling
Techniques”, IEICE Transactions on Fundamentals of Electronics,
Communications and Computer Sciences, vol. E87-A, no. 11, pp. 2973-2982,
November 2004.
[15] Michael L. Bushnell, Vishwani D. Agrawal, “Essentials of Electronic Testing:
Digital, Analog, and Mixed-Signal”, Kluwer Academic Press, Boston, 2000
[16] The MathWorks, Inc. http://www.mathworks.com, 2006.
[17] 羅華強,「類神經網路---Matlab 的應用」,清蔚科技,2001 年。
[18] 葉怡成,「類神經網路模式應用與實作」,儒林圖書公司,2003 年。
[19] Brglez, F., Fujiwara, H., “A Neutral Netlist of 10 Combinational Benchmark
Circuits and a Target Translator in Fortan”, Proc. of International Symposium on
Circuits and Systems, pp. 663-698, 1985
[20] Yang, S.,” Logic Synthesis and Optimization Benchmarks Version 3.0 Technical
Report”, Microelectronics Center of North Carolina, 1991.
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