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研究生:劉孟帆
研究生(外文):Meng-Fan Liu
論文名稱:以類比行為模型建立三角積分數位類比轉換器之非理想現象的研究
論文名稱(外文):On Analog Behavioral Modeling for ΣΔDAC with Non-Ideal Effect
指導教授:劉建男劉建男引用關係
指導教授(外文):Chien-Nan Jimmy Liu
學位類別:碩士
校院名稱:國立中央大學
系所名稱:電機工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2006
畢業學年度:94
語文別:中文
論文頁數:63
中文關鍵詞:行為模型數位類比轉換器由下而上
外文關鍵詞:behavioral modelbottom updigital to analog converter
相關次數:
  • 被引用被引用:1
  • 點閱點閱:347
  • 評分評分:
  • 下載下載:89
  • 收藏至我的研究室書目清單書目收藏:0
隨著CMOS製程技術迅速地進步,電晶體的大小不斷地變小,一片晶圓上的電晶體數目多達幾十億個,使得電路設計的複雜度提升到SoC(System on Chip)的階層。在SoC的時代裡,電路設計的趨勢逐漸走向包含數位電路以及類比電路的混合電路設計,處理如此龐大的設計,驗證的問題變得非常的困難,模擬所花費的時間也隨著增加,為了快速驗證設計者的電路,許多努力都致力於將電路提高到行為層級描寫,以加快此設計流程。過去這幾年來,當設計者在發展類比電路或是混合信號電路的時候,SPICE電路模擬器一直都是最基本的設計與驗証工具,但是隨著半導體技術的不斷發展、推出市場的快速要求(time to market)…等等,傳統的SPICE模擬器再也無法滿足先進電路的設計需求了。
此論文裡,我們提出了一套利用Verilog-A硬體描述語言建立ΣΔDAC類比電路的行為模型,並且利用由下而上(bottom-up)的驗證方法,將電路的非理想因素萃取出來,並建立了一套標準的參數萃取流程,使得我們的行為模型更接近實際傳統的電晶體層級(transistor level)的模擬結果,達到快速模擬又不失精確度的目的。
With the process technology innovating rapidly, the device size is continuing to scale down. In SoC era, traditional design techniques must be modified to solve the integration problems with over million gate counts in a single chip. The major design challenge is the issue of co-simulation speed to verify a mixed-signal system. Integrating all blocks at layout-level and running the low-level post-layout simulation become almost infeasible for modern large designs. Moreover, such traditional simulator like SPICE requires too much simulation time such that it cannot meet the designer’s demand due to the pressure of time to market. Therefore, building a behavioral model is necessary so that we could get the simulation results very soon.
In this thesis, we use hardware description language Verilog-A to build the behavioral models of ΣΔDAC and use them to estimate and handle these two integration issues. We present a bottom-up extraction flow to extract the characteristic parameters for ΣΔDAC behavioral models in a short time. Then, we adjust these parameters to consider the non-ideal effects such that the behavioral model could be much closer to the simulation results of SPICE.
第1章 序論 - 1 -
1.1 研究動機 - 1 -
1.2 由下而上(Bottom-up)行為模型的方法 - 4 -
1.3 論文組織 - 5 -
第2章 背景知識研讀 - 6 -
2.1 系統架構介紹 - 6 -
2.2 升頻濾波器(Interpolation Filter) - 8 -
2.3 三角積分調變器(Sigma-Delta Modulator) - 9 -
2.4 數位類比轉換器(D/A Converter) - 11 -
2.5 類比低通濾波器(Analog Lowpass Filter) - 12 -
2.6 非理想效應 - 15 -
第3章 ΣΔ DAC的類比行為模型 - 16 -
3.1 序論 - 16 -
3.2 理想的類比行為模型 - 17 -
3.2.1 數位類比轉換器 - 17 -
3.2.2 Biquad電路 - 20 -
3.2.3 DCT電路 - 24 -
3.3 非理想的類比行為模型 - 26 -
3.3.1 非理想因素及來源 - 26 -
3.3.2 參數萃取方法及流程 - 28 -
3.3.2.1 DC gain – Biquad電路 - 29 -
3.3.2.2 DC gain – DCT電路 - 32 -
3.3.2.3 迴轉率(Slew rate) - 35 -
第4章 模擬結果與分析 - 43 -
4.1 產生數位訊號 - 43 -
4.2 實驗結果比較 - 44 -
第5章 結論 - 50 -
參考文獻 - 51 -
[1]“Verilog-AMS Language Reference Manual Version 2.2”, Accellera, Nov. 2004.
[2]“CIC訓練課程 Mixed-Signal IC Design Kit Training Manual”, 國家晶片系統設計中心, July, 2003.
[3]R. Schrier, G. C. Temes, “Understanding Delta-Sigma Data Converters”, Wiley-IEEE Press, Nov. 8, 2004.
[4]G. I. Bourdopoulos, A. Pnevmatikakis, V. Anastassopoulos, T. L. Deliyannis, “Delta-Sigma Modulators: Modeling, Design and Applications”, Imperial College Press, Sep. 2003.
[5]“2005混合訊號式積體電路設計短期課程:Delta-Sigma Data Converters Design”, 混合訊號式積體電路設計聯盟, Sep. 2005.
[6]Chun-Hsien Su, “Analog Integrated Circuit Design Course”, 2006.
[7]Tai-Haur Kuo, “Advanced Analog IC Design for Communications Course”, 2003.
[8]R. Schaumann, M. E. V. Valkenburg, “Design of Analog Filters”, Oxford University Press, 2001.
[9]K. Martin, A. Sedra, “Effects of the Op Amp Finite Gain and Bandwidth on the Performance of Switched-Capacitor Filters”, IEEE Transactions on Circuits and Systems, vol. 28, Issue 8, Aug. 1981, pp. 822-829.
[10]E. Lauwers, K. Lampaert, P. Miliozzi, G. Gielen, “High-level design case of a switched-capacitor low-pass filter using Verilog-A”, Proceedings 2000 IEEE/ACM International Workshop on Behavioral Modeling and Simulation, Oct. 19-20, 2000, pp. 16-21.
[11]M. Vogels, B. De Smedt, G. Gielen, “Modeling and simulation of a sigma-delta digital-to-analog converter using VHDL-AMS”, Proceedings 2000 IEEE/ACM International Workshop on Behavioral Modeling and Simulation, Oct. 19-20, 2000, pp. 5-9
[12]H. Zare-Hoseini, O. Shoaei, I. Kale, “Precise Behavioral Modeling of High-Resolution Switched-Capacitor Delta-Sigma Modulators”, Proceedings of the 21th IEEE, Instrumentation and Measurement Technology Conference, vol. 2, May 18-20, 2004, pp. 1165-1169.
[13]P. Malcovati, S. Brigati, F. Francesconi, F. Maloberti, P. Cusinato, A. Baschirotto, “Behavioral Modeling of Switched-Capacitor Sigma-Delta Modulators”, IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 50, Issue 3, Mar 2003, pp. 352-364.
[14]J. Bingham, “Applications of a Direct-Transfer SC Integrator”, IEEE Transactions on Circuits and Systems, vol. 31. Issue 4, Apr. 1984, pp.419-420.
[15]Behzad Razavi, “Design of Analog CMOS Integrated Circuits”, McGraw-Hill, 2001.
[16]P. E. Allen, D. R. Holberg, “CMOS Analog Circuit Design”, Oxford University Press, 2002.
[17]M. Burns, G. W. Roberts, “An Introduction to Mixed-Signal IC Test and Measurement”, Oxford University Press, 2001, pp. 171-177.
[18]“On Behavioral Modeling for Phase-Locked Loop Circuit with Non-Ideal Effects”, 王裕謙, 國立中央大學電機工程研究所碩士論文, 中華民國九十三年六月.
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