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研究生:洪健鈞
研究生(外文):Jian-Jyun Hong
論文名稱:H.264/AVC之高效率框內預測模式選擇設計
論文名稱(外文):Design of High Efficiency Intra-Prediction Mode-Selection in H.264/AVC
指導教授:許鈞瓏
指導教授(外文):Chu-Lung Hsu
學位類別:碩士
校院名稱:國立東華大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2006
畢業學年度:94
語文別:英文
論文頁數:79
中文關鍵詞:框內預測
外文關鍵詞:Intra PredictioinH.264/AVC
相關次數:
  • 被引用被引用:0
  • 點閱點閱:197
  • 評分評分:
  • 下載下載:9
  • 收藏至我的研究室書目清單書目收藏:0
數位視訊科技已在我們的日常生活中扮演重要的角色,編碼效能
也隨著技術的演進而提升。在相同的品質下,H.264相較於之前
的標準能節省大約50%的位元率,但由於其具有相當複雜之編碼
技術及模式選擇,使得運算複雜度也遠高於先前的編碼標準,因
此如何設計高效能的運算模組與在不犧牲H.264/AVC之編碼效能
的前提下,降低其運算複雜度,為目前相當重要的課題。在本論
文中,我們提出快速框內預測模式選擇演算法和相對應的硬體架
構設計來有效的加速在H.264中模式選擇的編碼時間。
以區塊形式選擇、根據計算邊緣特性得到局部邊緣資訊和次取樣
的相稱運算為基礎。使得提出的IPMS 演算法能減少65%的編碼
時間,增加額外位元率低於3.7%,以及PSNR 減少不超過0.7dB。
依據IPMS 演算法,經由HDL 與Quartus II 驗證得知,所提出的
框內模式選擇的硬體架構,其使用的邏輯閘數約為33.7K。整體
效能評估說明了以IPMS 演算法為基礎所提出的硬體架構設計其
可靠度佳和可行性高。
Digital video technology has played an important role in our daily life. With the
evolution of video technology coding efficiency has been greatly improved. H.264 can
provides approximately 50% bit rate saving for equivalent perceptual quality relative to
the performance of prior standards. However, this efficiency comes with the cost of
much higher computational complexity than previous standards due to the complex
coding approaches and mode decision techniques. Thus, how to design high
performance functional units and reduce computational complexity without great
quantity of degradation in coding efficiency are deserved to be mentioned. In this
thesis, a fast intra-prediction mode-decision (IPMS) algorithm and the corresponding
hardware design are proposed to effectively speed up the encoding time for mode
decision in H.264/AVC.
Based on the block type selection approach, the local edge information obtained
by calculating edge feature parameters and sub-sampling of matching operations, the
proposed IPMS algorithm can reduce the encoding time over 65% considerably with
less than 3.7% extra bits used and no more than 0.7 dB PSNR sacrificed. The
hardware architecture design is implemented by using the Verilog HDL coding.
Through the Quartus II verification, the equivalent gate counts of the proposed
hardware architecture are about 33.7K. Verification results and performance
evaluation reveal that the reliability and feasibility of the proposed hardware design
based on IPMS algorithm.
CHAPTER 1 INTRODUCTION 1
1.1. Motivation 2
1.2. Organization for the Thesis 3
CHAPTER 2 OVERVIEW OF H.264/AVC 4
2.1. H.264 Encoder 5
2.1.1 Forward Dataflow Path 6
2.1.2 Reconstruction Dataflow Path 7
2.2. H.264 Decoder 7
2.3. Intra Prediction 8
2.3.1 Intra Prediction Mode 9
2.3.2 Mode Selection 14
2.4. Mode Selection Tehniques 18
2.4.1 Edge Information Technique 18
2.4.2 Subsample Technique 22
CHAPTER 3 HARDWARE ARCHITECTURE DESIGN OF INTRA PREDICTION 24
3.1. Algorithm Description 24
3.1.1 Best Mode Decision 25
3.1.2 Summary of the Operations 27
3.2. Hardware Realization 30
3.2.1 Block Type Selection 32
3.2.2 Edge Information 33
3.2.3 Intra Prediction Generator 35
3.2.4 SATD 46
3.2.5 Mode Desion 47
CHAPTER 4 PERFORMANCE EVALUATION 49
4.1. Simulation Results 49
4.1.1 Rate Distortion and Rate Coding Time Analysis 49
4.1.2 PSNR, Bit Rate and Speed-Up Ratio Discussion 54
4.1.3 Subjective Quality Observation 57
4.2. Verification Results 62
4.2.1 Block Type Selection Realization 62
4.2.2 Edge Information Realization 64
4.2.3 Intra Prediction Generator Realization 66
4.2.4 SATD Realization 70
4.2.5 Mode Decision Circuit Realization 71
4.3. Comparisons 73
CHAPTER 5 CONCLUSIONS AND FUTURE WORKS 75
5.1. Conclusions 75
5.2. Future Works 76
REFERENCES 77
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