臺灣博碩士論文加值系統

本論文提出一個應用於5.8 GHz無線區域網路的低雜訊放大器之設計。利用TSMC 0.18μm CMOS的製程，為了達到1伏特低電壓與低功率的需求，吾人利用轉換器回授中和化法來降低閘-汲極電容(Cgd)所產生的密勒效應，以進行放大器設計。首先本論文將詳細描述轉換器回授放大器設計的原理及方法，接著設計差動式單石轉換器的結構，除了利用電磁模擬程式模擬此元件高頻的特性，分析其電路特性，並利用集總元件來建立差動式轉換器的等效電路模型。接著將所得高頻模擬結果，置入放大器電路進行設計，研究與探討單石電感與轉換器的寄生效應及損耗與對電路影響。考量被動元件實際電磁模擬結果與最佳化設計後，本論文所使用的電路架構，經過電路模擬結果可達到功率增益為13.825 dB、雜訊指數約為2.7 dB、輸入損耗反射係數為-22.683 dB、輸出損耗反射係數為-13.834 dB、逆向隔離度為-38.343 dB及IIP3為6.8 dBm，最後並進行電路佈局與實驗討論。

In this thesis, we present the whole design of a low noise amplifier in a 0.18 μm CMOS process for 5.8 GHz wireless local area network application. To operate at 1V low-voltage supply and 16 mW low-power consumption, transformer-feedback technique is employed here to neutralize the gate-drain overlap-capacitance of a MOSFET, i.e., Miller effect. First in this paper, the design approach of the transformer-feedback LNA is described in detail. Second, differentially monolithic-transformer structure is designed, analyzed, and its lumped-element equivalent circuit model is also proposed to characterize its performance. Then, parasitic effect of lossy monolithic-inductor and transformer were studied and included in the simulation of the whole practical design. Their influences on noise and power gain are discussed and then circuit optimization is performed. The simulation results of final design show that the real design can achieve a power gain of 13.285 dB, noise figure of 2.7dB, input return loss of -22.683 dB, output return loss of -13.836 dB, reverse isolation of -38.343 dB, and input third-order intercept-point of 6.8 dBm. Finally, the low voltage supply LNA based on transformer-feedback technique and internal input-matching circuit is layouted and measurement set-up is implemented to verify its performance.

第一章 緒論 1
1.1 前言 1
1.2 研究動機 2
1.3 論文組織 4
第二章 射頻低雜訊放大器的原理 5
2.1 雜訊的種類與雜訊指數 5
2.2 積體電路內部的雜訊來源 8
2.3 穩定度與線性度的考量 11
2.4 降低Cgd影響之電路架構 14
第三章 轉換器回授之低雜訊放大器的設計分析 26
3.1 簡介 26
3.2 轉換器回授之低雜訊放大器分析推導 26
3.3 轉換器回授之低雜訊放大器設計 33
3.3.1 功率消耗決定之方法 33
3.3.2 電晶體寬度決定之方法 34
3.3.3 直流偏壓電路設計 36
3.3.4 匹配電路設計 37
3.3.5 最佳化雜訊阻抗設計 39
3.4 電路模擬結果 40
第四章 單石平面電感與轉換器的設計分析 55
4.1 簡介 55
4.2 單石平面電感設計與模擬結果 56
4.3 提升品質因數的方法 57
4.4 單石轉換器設計與模擬結果 58
4.5 轉換器模型之建立、分析與模擬 60
4.5.1 轉換器模型分析 60
4.5.2 轉換器模型模擬結果 66
4.6 總結 67
第五章 考慮被動元件寄生效應之設計、佈局與實驗考量 88
5.1 前言 88
5.2 實際匹配電路設計與模擬 88
5.3 實際電路之佈局與量測的方法 91
第六章 結論 107
參考文獻 109

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