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研究生:張博翔
研究生(外文):Po-hsiang Chang
論文名稱:加強型八位元微控制器及其系統晶片整合
論文名稱(外文):Enhanced 8-bit microcontroller and its SoC integration
指導教授:黃英哲黃英哲引用關係
指導教授(外文):Ing-Jer Huang
學位類別:碩士
校院名稱:國立中山大學
系所名稱:資訊工程學系研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2006
畢業學年度:94
語文別:中文
論文頁數:119
中文關鍵詞:微控制器運算加強晶片系統整合
外文關鍵詞:MicrocontrollerOperation enhancementSoC integration
相關次數:
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3C商品所代表的意義是—運算(Computation)、通訊(Communication)及消費性電子(Consumer Electronics)產品,其中,消費性電子產品躍升為高科技產業主流,近幾年來,消費性電子產品變為更強調運算與通訊功能的整合性產品,另外,輕、薄、短、小的趨勢也使得消費性電子產品內部的各類晶片都朝向高度集積化發展,上述趨勢對嵌入式半導體供應商帶來的難題就是:必須在不增加晶片面積的前提下,強化運算能力與功能整合。
本篇論文提出的想法為,在不改變微控器基本架構的前提下,加入運算加強的指令集,並分析各種不同的硬體實作方式所能達到的效果,判斷各種方式之中的優缺點,在實際考量上做一個取捨,期望能以最小的硬體成本,達到最大的加速效果,最後實作出一顆以低成本加強運算能力的微控制器。
本論文的研究結果可從兩個方向來探討,其一為單純加強微控器的運算處理能力上,加入運算加強指令集之後,可在不影響系統時脈的情況下,增加約10%的面積來減少各種特殊運算的執行時間約54%,亦或是在可容許的些微系統時脈下降:同樣增加約10%的面積及6.35%時脈下降之成本,達到減少各種特殊運算執行時間約59%,故效能提升顯著。第二個方向則是微控器加入嵌入式擬真器之後的改變。顯然的,除錯功能的加入並不會改變系統時脈,但面積增加約112%,成本驚人,故可得知在嵌入式擬真器的加入方法之中,應採用全boundary scan cell方式來實作,以保持微控器及嵌入式擬真器之間的獨立性。
The word “3C products” means computation, communication and consumer electronics products. Particularly, consumer electronics products become one of the most important part of high technology industry. Recently, the properties of consumer electronics products tend to integrate powerful computation and communication abilities. Further more, the trend of more light, thin, short and small makes every kind of IC inside consumer electronics products highly integration. This tendency describe above brings embedded semiconductor providers a difficult problem. That is, we must improve the computation ability and function integration without increasing area overhead.
The proposed method of this thesis is adding computation enhanced instructions in original instruction set without change basic architecture of microprocessor. Further, make a better design choice after analyzing different implement ways and considering their trade off between performance and cost. The goal is producing a powerful microprocessor which is improved the most with the least overhead.
There are two directions in the result of this thesis. One is pure enhancing microprocessor computation ability. About 54% special operation execution time is reduced by adding operation enhanced instructions, but only taken 10% area cost. However, if 6.35% system frequency speeddown is acceptable, about 59% special operation execution time could be reduced. The other is the phenomenon after integrating In-Circuit Emulator (ICE) in microprocessor. Apparently, integrating debug mechanism doesn’t change timing of whole system. However, it makes a great deal of circuit area overhead about 112%. This result shows that a system needs keep individual characters between microprocessor and ICE. A batter method of integrating ICE in system is using boundary scan cell in whole system.
Chapter 1 Introduction
1.1 背景
1.2 動機
1.3 研究方法
1.4 主要貢獻
1.5 論文架構
Chapter 2 Related work
2.1 各種常見微處理器實用性及架構
2.1.1 PIC16C 架構
2.1.2 8051架構
2.2 其他對於運算加強需求的解法
2.2.1 在系統中加入DSP或ASIC
2.2.2 加入增強型指令集
Chapter 3 Implementation of PIC16C-like microprocessor
3.1 PIC16C相容指令集
3.2 微控器架構
3.2.1 微控器管線架構
3.2.2 中斷控制單元
3.2.3 定址模式
3.3 微控器核心模組
3.3.1 Instruction fetch & instruction decode stage
3.3.2 Execute & write back stage
3.4 Memory mapped register
Chapter 4 Cost effective operation enhancement
4.1 運算增強指令集
4.2 自動化指令編碼演算法
4.3 運算加強指令實作方式與分析
4.3.1 乘法
實現方式一:實作單一週期乘法器
實現方式二:使用PIC原硬體架構實現乘法指令
實現方式三:串聯移位電路及加法器構成乘法器
使用多重週期路徑(multicycle path)來實現乘法指令的考量
乘法實作數據分析與決策
4.3.2 十六位元運算
4.3.3 查表指令
4.3.4 十進制調整
4.4 運算加強後微控器架構
4.4.1 微控器核心模組的改變
4.4.2 Memory mapped register的改變
4.4.3 軟體工具鏈的改變
4.4.4 微控器核心最長路徑分析
4.5 合成結果及分析— ALU運算能力加強
4.6 管線控制暫存器精簡
4.6.1 原始架構 — MEMCU full pipeline architecture
4.6.2 管線控制暫存器精簡方法
4.6.3 管線控制暫存器精簡結果
4.7 合成結果與分析 — 微控制器核心效率與成本
Chapter 5 SoC Integration
5.1 系統晶片架構
5.2 嵌入式擬真器整合方法
5.2.1 ICE架構
5.2.2 掃描鏈
5.2.3 時脈同步模組
5.2.4 系統整合架構
5.2.5 SYS8MI與ICE間溝通機制
5.3 合成結果及分析 — 系統晶片整合
5.4 應用實例
Chapter 6 Software development environment
6.1 C-complier
6.2 Assembler
6.3 Simulator
6.4 ICE control software
6.5 Interface
Chapter 7 RTL verification and FPGA prototyping
7.1 RTL level軟硬體共同驗證流程
7.2 FPGA prototype驗證
7.2.1 實驗板介紹 — Nios Development Board (Cyclone Edition)
7.2.2 FPGA prototype驗證流程
Chapter 8 Conclusion
參考文獻(References)
附錄A 運算加強指令集
附錄B Memory map address table
附錄C Signals in internal scan chains
附錄D Signals in boundary scan chains
附錄E Components of Nios Development Board
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