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研究生:謝曜任
研究生(外文):Yao-Ren Xie
論文名稱:適用於多電壓系統的低功率對應方法
論文名稱(外文):Low Power Mapping Methodology for Multi-voltage System
指導教授:鄺獻榮
指導教授(外文):Shiann-Rong Kuang
學位類別:碩士
校院名稱:國立中山大學
系所名稱:資訊工程學系研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2006
畢業學年度:94
語文別:英文
論文頁數:60
中文關鍵詞:多重電壓對應方法
外文關鍵詞:Multi-voltagemapping methodologylow power
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  • 被引用被引用:0
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  • 下載下載:19
  • 收藏至我的研究室書目清單書目收藏:0
隨著系統晶片的快速發展,使得低功率的設計也變成了重要的課題。為了解決這個問題,電路方面提供了多電壓的方式來降低工作的功率消耗。在軟體工具則是決定每一個工作要在那種電壓下執行,使得整體功率消耗能達到最少。在本論文中,我們設計了一個基因演算法來解決工作電壓對應問題,此演算法主要目標是在多重電壓的系統下,考慮時間限制或是功率限制來求得較好的解。為了應用在系統上,我們建立了一個設計流程並且把基因演算法內嵌進去。
我們將這個基因演算法應用在二個範例上。第一個範例是多重電壓可重置式處理器,這顆處理器提供了可變執行模式和可變執行電壓,可變執行模式讓平行度較高的工作減少執行時間,可變執行電壓則讓一些工作降低工作電壓來減少功率消耗。在有效能限制下,我們利用基因演算法來決定每一個工作要在那種模式下執行以達到最低功率消耗。另一個範例是多電壓多處理器的工作排程。同樣在效能限制下,我們先利用線性排程決定工作的排程,再利用基因演算法來決定每一個工作的電壓來降低功率消耗。實驗結果顯示,利用基因演算法能有效降低功率消耗。
Since the development of SoC is very fast, how to reduce the power consumption of SoC has become a very important issue. To overcome the issue, the hardware circuit provides multi-voltage method to reduce task power consumption. On the other hand, the software tool decides the task voltage to minimize the total power consumption. In this thesis, we developed a genetic algorithm to solve the voltage mapping problem of multi-voltage systems. This goal of this genetic algorithm is to consider the time constraints or power constraints in the multi-voltage system to find the better solution. In order to apply genetic algorithm to solve voltage mapping problem, we build a compilation flow that embeds in the genetic algorithm.
To demonstrate the efficiency of proposed approach, we apply compilation flow to two examples. One is multi-voltage reconfigurable processor system. The processor in the system provides multi-mode and multi-voltage. The multi-mode can reduce the execution time of tasks with high parallelism. Multi-voltage can reduce the power consumption of task by decreasing voltage. We use genetic algorithm to choose task mode to achieve the performance goal. Another is multiple multi-voltage processors. We use list-scheduling to find the task schedule and use genetic algorithm to choose the task voltage. This method can reduce total power consumption. According to the experimental results, the proposed genetic algorithm can reduce the power consumption efficiently.
CHAPTER 1 . INTRODUCTION 1
1.1 BACKGROUND 1
1.2 PROBLEM DESCRIPTION AND MAIN CONTRIBUTIONS 1
1.3 THESIS ORGANIZATION 2
CHAPTER 2 . RELATED WORKS 4
2.1 SOFTWARE ENVIRONMENT OVERVIEW 4
2.1.1 SUIF2 4
2.1.2 Machine SUIF 7
2.1.3 Machine SUIF for ARM Platform 10
2.2 TIME AND POWER ESTIMATION METHODS FOR MULTI-VOLTAGE SYSTEM 15
CHAPTER 3 . GENETIC ALGORITHM FOR MULTI-VOLTAGE TASK MAPPING 18
3.1 DEFINITION 18
3.2 CONCEPT OF GENETIC ALGORITHM 18
3.3 FLOW OF GENETIC ALGORITHM 20
3.4 EXPERIMENTAL RESULT 25
CHAPTER 4 . APPLYING GENETIC ALGORITHM TO A MULTI-VOLTAGE RECONFIGURABLE PROCESSOR SYSTEM 35
4.1HARDWARE DESCRIPTION 35
4.1.1 The Reconfigurable Component 37
4.1.2 The RC Array 39
4.1.3 The Reconfigurable DMA 41
4.1.4 The Reconfigurable Controller and the Context Memory 41
4.1.5 Software and Hardware Co-execution 42
4.1.6 Mapping Function Units for the Normal Computation onto the RC Array 44
4.1.7 Multi-voltage Mode 45
4.2 PROBLEM DESCRIPTION 45
4.3 MAPPING FLOW OF SOFTWARE TOOL 48
4.3.1 Dataflow Analysis 49
4.3.2 Operation scheduling 49
4.3.3 Performance and Power (2P) Estimation 49
4.3.4 Genetic Algorithm 50
4.3 EXPERIMENTAL RESULT 50
CHAPTER 5 . APPLYING THE GENETIC ALGORITHM TO MULTIPLE MULTI-VOLTAGE PROCESSORS 51
5.1 PROBLEM DESCRIPTION 51
5.2 MAPPING FLOW 54
5.2.1. Task graph generator 55
5.2.2. List scheduling 56
5.2.3. Genetic algorithm for task voltage selection 56
5.3 EXPERIMENTAL RESULT 57
CHAPTER 6 . CONCLUSION 58
REFERENCE 59
[1] T. D. Burd, T. Pering, A. Stratakos, and R. Brodersen, “A dynamic voltage-scaled microprocessor system,” in IEEE Int. Solid-State Circuits Conf., vol. 466, pp. 294–295, Feb. 2000.
[2] W. Namgoong, M. Yu, and T. Meng, “A high-efficiency variable-voltage CMOS dynamic dc-dc switching regulator,” in Proc. IEEE Int. Solid-State Circuits Conf., vol. 489, pp. 380–381, Feb. 1997.
[3] Tadahiro KURODA, “Low Power CMOS Design Challenges” in IEICE Trans. Electron., vol. E84-C, no.8, Aug. 2001.
[4] V.Von Kaenel, P. Macken, and M. G. R. Degrauwe, “A voltage reduction technique for battery-operated systems,” in IEEE J. Solid-State Circuits, vol. 25, pp. 1136–1140, Oct. 1990.
[5] P. Macken, M. Degrauwe, M. Van Paemel, and H. Oguey, “A voltage reduction technique for digital systems,” in Proc. IEEE Int. Solid-State Circuits Conf., pp. 238–239, Feb. 1990.
[6] M. Horowitz, “Low power processor design using self-clocking,” in Workshop on Low-Power Electronics, Aug. 1993.
[7] G.-Y. Wei and M. Horowitz, “A low power switching power supply for self-clocked systems,” in Proc. Int. Symp. Low Power Electronics Design, pp. 313–317, Aug. 1996.
[8] T. D. Burd, T. Pering, A. Stratakos, and R. Brodersen, “A dynamic voltage scaled microprocessor system,” in IEEE J. Solid-State Circuits, vol.35, no. 11, pp. 1571–1580, Nov. 2000.
[9] G. Qu, “What is the limit of energy saving by dynamic voltage scaling?,” in IEEE/ACM Int. Conf. Computer-Aided Design., pp. 560–563, 2001.
[10] K. Usami and M. Igarashi, “Low-power design methodology and applications
utilizing dual supply voltages,” in Proc. Asia South Pacific Design Automation Conf., pp. 123–128, Jan. 2000.
[11] Gang Qu and Miodrag Potkonjak, “Techniques for Energy-Efficient Communication Pipeline Design,“ in IEEE Trans. On Very Large Scale Int. (VLSI) Systems, vol. 10, no. 5, Oct. 2002.
[12] Sinha, A., Chandrakasan, A. “JouleTrack - A Web Based Tool for Software Energy Profiling,” in Proc. of the 38th Design Automation Conf., Las Vegas, June 2001.
[13] The SUIF Compiler System. http://suif.stanford.edu/suif/suif2/
[14] The Machine SUIF Compiler Infrastructure. http://www.eecs.harvard.edu/hube/software/software.html
[15] Machine SUIF Back-end for the ARM Architecture
http://lap.epfl.ch/dev/machsuif/arm_backend/
[16] I. Hong, D. Kirovski, G. Qu, M. Potkonjak, and M. B. Srivastava, “Power Optimization of Variable-Voltage Core-Based Systems,” in IEEE Trans. on Computer-Aided Design, 18(12):pp.1702-1714, Dec. 1999.
[17] F. Yao, A. Demers, and S. Shenker, “A scheduling model for reduced CPU energy,” in IEEE Symposium on Foundations of Comp. Science, pp. 374-382, 1995.
[18] M. T. Schmitz and B. M. Al-Hashimi, “Considering power variations of DVS processing elements for energy minimisation in distributed systems,” in Proc. ISSS, 2001, pp. 250-255.
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