臺灣博碩士論文加值系統

隨著諸如手提式電腦、手機等可攜式電子產品以及各種通訊器材的出現，功率的消耗問題已經變成超大型積體電路設計中一個重要的研究主題。此外，乘法器在數位信號處理及多媒體電路設計中，不但是一個不可或缺的基本電路區塊，同時也扮演著一個多媒體電路功率消耗的瓶頸。乘法器本身功率的消耗，深深地影響整個多媒體系統的功率消耗。因此，如何將乘法器本身的功率消耗減少到最小，對一個超大型積體電路的低功率設計來說是很重要的。另外，一個有效率的乘法器，對於DSP系統和計算機體系架構來說是非常需要的。在大多數的DSP和多媒體系統中，乘法器的輸入值範圍通常非常小，而且輸出乘積的LSP(Least Significant Part)數個位元通常會被略去，用來避免位元數的成長。
基於上述這些特徵，在這篇論文中，我們提出一個具低功率設計的有號數乘法器，透過偵測Dynamic range的方法，動態的偵測輸入值範圍的大小來關閉不需使用的元件，以減少這些元件的switch達到減少功率消耗的目的。另外，我們也透過重置輸出精確度，以及管線化等方法使乘法器的執行更有效率。我們將這些技巧應用到兩種不同架構的乘法器上：Array-based multiplier 以及Booth-based multiplier。透過在邏輯閘階層的初步分析，我們得知，在Array-base的架構下，透過少量電路面積的增加，可以節省的功率最高約為47%; Booth-based multiplier的架構之乘法器則可節省最高約30%的功率消耗。
同時，為了符合系統產品開發的低成本、高獲利目標以及縮短開發時間，我們設計了一個自動產生器，透過使用者介面由使用者自訂乘法運算的輸入大小、低功率架構型態以及所需精確度來產生我們的低功率乘法器硬體架構。

With the emergence of portable computing and communication systems, power consumption has become one of the major objectives during VLSI design. Furthermore, multipliers are always fundamental building blocks and the bottleneck in terms of power consumption in many DSP and multimedia applications. Therefore, it is crucial to minimize the power consumption of multipliers in the system for low-power VLSI design. Besides, energy-efficient multiplier is greatly desirable for DSP systems and computer architectures. In many of these systems, the dynamic-range of input operands for multiplier is usually very small. In addition, the least significant bits of output products are often rounded or truncated to avoid growth in word size.
Based on these features, this thesis presents an approach to design low-power and reconfigurable signed pipelined multipliers. The approach dynamically detects input range of the multiplier and disables the switching operations of non-effective ranges to decrease the power consumption. Moreover, the proposed approach can reconfigure the output precision of the multiplier to save power consumption.
We apply this approach to two architectures: array-based and Booth-based architecture. Experimental results show that the proposed array-based pipelined multiplier leads to up 47% power saving and Booth-based multiplier leads to up 30% power saving with a little additional area and delay overheads.
Besides, in order to accord with the low cost and high profit-making goal of systematic products and shorten construction period, we have designed a low-power multiplier generator. User could use the user interface to configure the multiplier size, low power architecture and the precision that user need. The generator will create the hardware architecture of low-power multiplier automatically.

CHAPTER 1 INTRODUCTION 1
1.1 Research Motivation 1
1.2 Related Survey 3
1.3 Other Background 4
1.3.1 Prime Power 4
1.3.2 NanoSim 7
1.3.3 Soc Encounter 10
1.3.4 IMDCT 12
1.3.5 Speech 13
1.4 Thesis Organization 14
CHAPTER 2 CONVENTIONAL MULTIPLIER 15
2.1 Array-based multiplier 15
2.1.1 Baugh-Wooley multiplier 15
2.1.1.1 Carry Save Adder 19
2.1.1.2 Carry Lookahead Adder 20
2.2 Booth Multiplier 21
2.2.1 Recoding 22
2.2.2 Partial product generator 26
2.2.3 Compression tree 29
2.2.3.1 Wallace tree 29
2.2.3.2 Dadda tree 30
2.2.4 Faster adder 33
CHAPTER 3 ARRAY-BASED LOW POWER MULTIPLIER 34
3.1 Partially Guarded Computation 35
3.1.1 Dynamic Range Detector 35
3.1.2 Sign Extension Logic 39
3.2 Truncated Multiplication 41
3.2.1 Error Analysis 42
CHAPTER 4 BOOTH LOW POWER MULTIPLIER 46
4.1 Partially Guarded Computation 47
4.1.1 Dynamic Range Detector 47
4.1.2 Sign Extension Logic 50
CHAPTER 5 ANALYSIS AND RESULT – PrimePower 52
5.1 Version introduction 52
5.1.1 Proposed Array-based multiplier 53
5.1.2 Proposed Booth-based multiplier 54
5.2 Result 58
5.2.1 Proposed array-based multiplier 58
5.2.2 Proposed Booth-based multiplier 60
CHAPTER 6 ANALYSIS AND RESULT – Post layout 61
CHAPTER 7 LOW-POWER MULTIPLIER GENERATOR 64
CHAPTER 8 CONCLUSION AND FUTURE WORK 67
8.1 Conclusion 67
8.2 Future work 67
Bibliography 68

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[11]The specification for PrimePower