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研究生:林騏宏
研究生(外文):Chi-Hung Lin
論文名稱:用於嵌入式系統之匯流排資料追蹤分析器
論文名稱(外文):An On-Chip Bus Trace Analyzer for SoC’s
指導教授:黃英哲黃英哲引用關係
指導教授(外文):Ing-Jer Huang
學位類別:碩士
校院名稱:國立中山大學
系所名稱:資訊工程學系研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2006
畢業學年度:94
語文別:中文
論文頁數:118
中文關鍵詞:匯流排壓縮追蹤除錯
外文關鍵詞:compressionbustracedebug
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追蹤技術表示系統執行時所產生的相關訊號資料可以被即時追蹤裝置擷取並且傳回電腦後作後端的觀察和分析。隨著系統設計越來越複雜,便需要一個更先進的追蹤方法來取代過去只以處理器為主的追蹤。除此之外,由於目前即時的系統追蹤資料過於龐大,便需要適當的壓縮器來簡化追蹤資料。在本論文中,我們提出一個用於嵌入式系統的晶片匯流排追蹤分析器。這個追蹤分析器允許去收集準確、連續與無限長度的資料參考,而不會去影響匯流排系統的運作。我們的方法包括兩個階段:(1) 時間/訊號抽象層次 (2) 資料簡化。並且說明如何設計和實作這個晶片匯流排追蹤分析器。透過使用著不同的組態可以提供不同的除錯方向使用。最後,在實驗中我們針對AMBA系統下可達到99%的追蹤壓縮率。因此,透過這個匯流排追蹤分析器可以大幅增強除錯能力。
Tracing represents that the information which are generated from the system can be collected for later observation and analysis. Because the SoC design becomes more and more complex, an advanced tracing is needed instead of processor tracing only. However, the generation rate and the size of real time system traces are so huge such that the compressor for tracing is needed. In this thesis, we purpose an on-chip bus trace analyzer for SoC’s. This trace analyzer can allowed to perform accurate, successive trace collection in an unlimited time and can be used in various embedded system without influencing the operation of the bus system. The approach consists of two stages: (1) timing/signal abstraction stage and (2) trace reducing stage. And we show how to design and implement the on-chip bus trace analyzer. It can be also configured by users for different debugging uses. The experimental results show that this bus trace analyzer can reach a good compression ratio of 99% for AMBA system. Hence, by utilizing this trace analyzer, the support for debugging can be more powerful than existing method.
Chapter 1. Introduction 1
1.1 研究動機 1
1.2 研究背景 1
1.3 研究方法 3
1.4 主要貢獻 6
1.5 論文組織 6
Chapter 2. Related Work 8
2.1電路擬真模擬器(In-Circuit Emulator; ICE) 8
2.1.1 On-Chip Debugging技術簡介 8
2.1.2 On-Chip In-Circuit Emulator (ICE) 的硬體設計原理 9
2.1.3 ICE和微處理器的整合方式 15
2.2監測 (Monitor) 技術 16
2.2.1 MAMon 16
2.2.2 Monitor-Based Test 17
2.3位址追蹤壓縮技術 19
2.3.1 Packed Differential Address and Time Stamp (PDATS) 19
2.3.2 PDI 22
2.3.3 Stream-Based Trace Compression (SBC) 23
2.3.4 Locality-Based Online Trace Compression (LBTC) 25
2.3.5 Value Prediction-Based Compression (VPC) 27
2.3.6 ARM ETM 29
2.4系統除錯方式的比較 30
2.5無失真壓縮演算法 31
2.5.1 Huffman Encoding 31
2.5.2 Arithmetic Encoding 31
2.5.3 Lempel-Ziv Encoding 32
Chapter 3. Bus trace analyzer architecture 33
3.1即時晶片匯流排追蹤分析器的基本原理 33
3.1.1 Monitor 34
3.1.2 Trace reducing 34
3.2追蹤分析器的設計和架構 36
3.2.1 Monitor Stage (Timing and Signal Abstraction Stage) 37
3.2.2 Trace Reducing Stage 45
3.2.3 Packer and FIFO Module 57
3.2.4 Trace Data Stored in On-Chip Memory 61
3.2.5 ICE Related Module 63
3.3 Summary 67
Chapter 4. Experimental Results 68
4.1實驗方法和壓縮率分析 68
4.2 追蹤分析器腳位分析 77
4.3 On-Chip Memory對應追蹤深度之分析 81
4.4 個別模組功能之實驗分析 84
4.4.1 Monitor Stage (Timing and Signal Abstraction Stage) 84
4.4.2 Program address 壓縮器 88
4.5 硬體合成 90
Chapter 5. Verification and Application 92
5.1 基本驗證策略 92
5.1.1 Coding Style Checking 92
5.1.3 自動化驗證 94
5.1.3 Coverage Analysis 96
5.2 FPGA實作及驗證 96
5.2.1 Basic verification - Bus Function Model 97
5.2.2 Real application - 3D graphic acceleration 101
Chapter 6. Conclusion 105
Chapter 7. Future Work 106
References 108
[1]IEEE Industry Standards and Technology Organization (IEEE-ISTO): IEEE-ISTO 5001 1999, the Nexus 5001 Forum Standard for a Global Embedded Processor Debug Interface, available at http://www.nexus5001.org/
[2]IEEE Std 1149.1, IEEE Standard Test Access Port and Boundary-Scan Architecture, IEEE Computer Society, New York, 1990
[3]Mohammed El Shobaki and Lennart Lindh, “A Hardware and Software Monitor for High-Level System-on-Chip Verification,” Proc. of International Symposium on Quality Electronic Design, 26-28 March 2001, pp.56-61
[4]Hue-Min Lin, Chia-Chih Yen, Che-Hua Shih and Jing-Yang Jou, “On Compliance Test of On-Chip Bus for SoC,” Proc. of ASP-DAC, Jan. 2004, pp. 328-333
[5]Eric E. Johnson, Jiheng Ha, and M.Baqar Zaidi, “Lossless Trace Compression,” IEEE Trans. on Computers, vol. 50, no. 2, Feb. 2001, pp. 158-173
[6]A. Milenkovic, M. Milenkovic, "Exploiting Streams in Instruction and Data Address Trace Compression," Proceedings of the IEEE 6th Annual Workshop on Workload Characterization, Austin, TX, USA, October 27, 2003, pp. 99-107
[7]Yue Luo and Kurian John, “Locality-Based Online Trace Compressoion,” IEEE Trans. on Computers, vol. 53, no. 6, June 2004, pp. 723-731
[8]Martin Burtscher, Llya Ganusov, Sandra J. Jackson, Jian Ke, Paruj Ratanaworabhan, and Nana B. Sam, “The VPC Trace-Compression Algorithms,” IEEE Trans. on Computers, vol. 54, no. 11, NOV. 2005, pp. 1329-1344
[9]ARM Corp. Web Site, available at http://www.arm.com
[10]Gallager, R.G., “Variations on a Theme by Huffman,” IEEE Transactions Information Theory, IT-24, 1978, pp. 668-674.
[11]Witten I.H., Neal, R.M., and Cleary, J.G., “Arithmetic Coding for Data Compression,” Communication Of the ACM, vol.30, No. 6, JUN. 1987, pp. 520-540.
[12]Welch, T.A., “A Technique for High-Performance Data Compression,” Computers, vol. C-17, no.6, 1984, pp.8-19.
[13]I. J. Huang, C. F. Kao, H. M. Chen, J. N. Ruan and T. A. Lu, "A Retargetable Embedded In-Circuit Emulation Module for Microprocessors," IEEE Design and Test of Computers, July/August 2002, pp. 28-38
[14]賴奇劭, “Architecture Variations of ARM7 Microprocessors,” 國立中山大學資訊工程研究所碩士論文
[15]黃世明, “Real-Time Address Trace Compressor for Embedded Microprocessors,” 國立中山大學資訊工程研究所碩士論文
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