臺灣博碩士論文加值系統

在本論文中，我們製作出一種含優質本體縛點(body tie)之TFT元件。傳統的TFT元件在製程上通常使用浪費太大面積之本體縛點，且元件本身也因埋藏層 (buried oxide)熱傳導係數不佳而有嚴重的自體加熱效應(self-heating effect)，這些不理想之因素將導致元件可靠度(reliability)及ICs的集積度 (packing density)下降；因此我們提出類似薄膜電晶體(TFT)底部閘極(bottom gate)的架構，來達成優質本體縛點；不但源、汲極能自動升起且有助於3D立體製程技術的發展；同時為了抑制短通道效應及降低漏電流，我們挖除大部分之PN接面面積，形成超薄型薄膜(ultra-thin film)的本體；此外，我們在底部閘極兩旁形成適當厚度的邊襯(spacer)讓源、汲極不靠得太近，可減少米勒電容效應(Miller''s capacitance effect)。
根據ISE TCAD 9.5模擬發現，含優質本體縛點之SOI元件，能紓緩載子在通道中所衍生出來的〝自體加熱效應〞及有效消除因撞擊游離 (impact ionization)在輸出特性曲所造成的扭結(kink)現象，提高元件崩潰電壓與可靠度。雖然趨動電流因寄生電阻而略降，但在飽和區之輸出曲線卻是平滑的；而元件之短通道效應也因挖除過多之PN接面面積，形成超薄型薄膜的本體而被抑制，使得元件性能提升。

In this thesis, a bottom gate TFT with smart body tie device is realized, For a PDSOI devices, which usually uses large layout areas of body ties, and it has self-heating effect resulting from the buried oxide between the silicon film and substrate, which has a lower thermal conductivity.
In order to suppress the short channel effect and reduce leakage current, we dug out in advance the PN junction to formed the ultra thin film body, besides, in order to reduce Miller''s capacitance effect we formed enough thickness of spacer at both sides of the bottom gate and let the source and the drain region do not too closer nearly.
According to the simulation results of ISE TCAD, the TFT with smart body tie device can alleviate self-heating effect and can achieve kink-free at output characteristic curve due to hot carriers by impact ionization and enhance the breakdown voltage of the device. Although the drive current of the TFT device lower than conventional TFT due to the parasitic resistance in the body region, the output characteristic curve is smooth in the saturation zone; the device suppress the short channel effect and improve the performance of the device due to most areas of PN junction are dug out.

第一章 導論 1
第二章 新元件結構模擬 5
2-1 四種結構 (bulk_BG、SBT、UTB、UTBSBT) 輸入特
性曲線模擬 5
2-2 短通道效應整理 (short channel effect) 10
2-3 浮體效應 (floating body effect) 13
2-4 自體加熱效應 (self heating effect) 19
2-5 模擬結論 26

第三章 新元件結構的設計與製作 27
3-1 標準第零層製作 28
3-2 成長burried oxied與定義閘極 30
3-3 沉積閘極氧化層 32
3-4 定義主動區域 33
3-5 形成源、汲極區域 34
3-6 形成ultra-thin body 34
3-7 定義contact hole區域形成smart body tie 35
3-8 金屬連線 36
第四章 實作結果與討論 38
4.1 IDS － VGS 特性曲線 38
4.2 IDS － VDS特性曲線 39
4.3 實作元件 cross section SEM 45
4.4 結論 47
第五章 結論與未來發展 48
Reference 49
附錄 A : Layout 圖 54
B : 本篇論文獲得中華民國專利 55
C: 投稿的會議論文 56

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