臺灣博碩士論文加值系統

本論文提出了一個新型之混合式正交極座標調制發射機架構，此架構應用高效率功率放大器，如E類功率放大器，以達到高效率且適用於多模發射之目標。混合式正交極座標調制架構採用正交調制訊號驅動射頻功率放大器之輸入端，並以高效率S類調制器調制功率放大器之電源端。由於正交調制訊號與S類調制器均具有波包訊號可能導致雙重波包調制現象，故須發展數位預失真技術以改善此現象所導致之訊號失真。搭配預失真器之混合式正交極座標調制架構可降低直流功率消耗與輸入射頻訊號之饋入穿透現象，以實現高功率增加效率與高線性度之射頻發射機。

This dissertation presents a hybrid quadrature polar modulator (HQPM) to drive the power amplifier (PA) highly efficiently in a wireless RF transmitter with good potential for multi-mode operation. For enhancing the efficiency, a Class-E PA is used in the transmitter. The HQPM consists of a quadrature modulator for processing the RF modulated carrier and a Class-S modulator for processing the supply-voltage signal. The quadrature modulator and the Class-S modulator deliver the output signals with envelope variation before being inserted into the RF-input terminal and the supply-voltage terminal of Class-E PA, respectively, causing the double envelope modulation to distort the modulated RF signal at the PA output. Therefore, a digital predistorter is proposed to be embedded in the HQPM for compensation. The use of such predistorted HQPM techniques can help reducing the average DC and RF input powers and the output feed-through levels so as to enhance power added efficiency and adjacent channel power rejection quite remarkably.

1 Introduction 1
1.1 Research Motivation 1
1.2 Transmitter Architectures 3
1.2.1 Quadrature Modulation-Based Transmitter 3
1.2.2 Linear Transmitters Using Switching Mode PAs 4
1.2.3 Hybrid Quadrature Polar Modulation Architecture 7
1.3 Overview of Dissertation 10
2 DSM-Based Class-S Modulator 12
2.1 Class-S Modulator Architecture 12
2.1.1 Introduction to Class-S Modulator 12
2.1.2 Delta-Sigma Modulator 13
2.2 Class-S Modulator Design and Implementation 15
2.2.1 System Quality Analysis 15
2.2.2 Circuit Implementation 17
3 Class-E Power Amplifier 21
3.1 Class-E Power Amplifier Design 21
3.1.1 Design Consideration 21
3.1.2 Circuit Analysis 22
3.2 Analytical and Simulated Results 26
3.3 Effects of DC-feed and Bondwire Inductances 29
3.4 Circuit Implementation 31
4 Baseband Processor with Predistortion Scheme 34
4.1 Digital Predistorter 34
4.2 Coordinate Rotation Digital Computer 37
4.3 Baseband Processor 41
5 System Analysis and Experimental Results 45
5.1 System Parameters Analysis 45
5.1.1 Output Signal Quality 45
5.1.2 Path-Delay Mismatch 47
5.1.3 Average Transmit Efficiency 48
5.2 Simulated and Experimental Results 49
6 Conclusions 56
Bibliography 58

Appendix 67

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