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研究生:高聿謙
研究生(外文):Yu-Chien Kao
論文名稱:一個在多媒體系統單晶片平台上的H.264/AVC主要規範編碼器的研發
論文名稱(外文):Development of A Main Profile H.264/AVC Encoder on A Multimedia SOC Platform
指導教授:林永隆林永隆引用關係
指導教授(外文):Youn-Long Lin
學位類別:碩士
校院名稱:國立清華大學
系所名稱:資訊工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2006
畢業學年度:94
語文別:英文
論文頁數:34
中文關鍵詞:H.264編碼器
相關次數:
  • 被引用被引用:0
  • 點閱點閱:150
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  • 下載下載:9
  • 收藏至我的研究室書目清單書目收藏:0
我們利用我們現有的矽智財以及系統研發方法在一個多媒體的單晶片平台上面提出了一個 H.264/AVC主要規範編碼器。
在這個編碼器中我們使用了一個可以根據畫面類型彈性調整流水線操作階層數量的架構。我們使用了一個改良過後的模式決策器使我們的編碼器可以達到與參考軟體近乎相同畫質。我們使用了四個特別的記憶體存取裝置來處理我們對於編碼器外面記憶體的存取,並且在存取裝置中使用了一種預先讀取的機制來加強我們的效能。在畫面之間的影像預測,我們使用了一個可以減少記憶體存取次數的機制,來減少所需要的頻寬。同時我們使用了一種在矽智財間直接連結的架構來加強我們的效能。我們同時提出了我們在平台上所需要軟體的工作流程圖,以及介紹我們的編碼器如何與系統的架構溝通。
在完成之後我們的編碼器可以在我們的實驗平台上以每秒三十張畫面的速度下即時編碼 352 x 288畫素大小的影像。利用上述所提出的特性,我們的編碼器在平台下的工作頻率為18百萬赫茲並且可以燒入一個六百萬邏輯閘大小的現場可程式化邏輯閘陣列。與參考軟體相比較,我們的編碼器在速度上有約三百三十倍以上的提昇。
We propose an H.264/AVC main profile encoder based on our in-house IP-level and system-level degign methodology targeted towards a multimedia SOC platform. We employ a flexible four-stage pipelined architecture to enhance the performance. We use a modified mode decision cost formula which can achieve almost the same video quality as that of the reference software. We use multiple memory fetch units to access external memory. For inter prediction, we employ a memory reuse mechanism to reduce memory traffic. We also use direct connection between certain IP to boost the performance. After implementation, our design can real-time encode the video of 352x288 pixels with 30 fps into an H.264 main profile video stream on our platform. With the proposed special mechanisms, our design only needs to run at 18 MHz and can be burned into a 6M gate count FPGA. Comparing with the performance of the reference software, our is 300 times faster with only a little video quality tradeoff.
Abstract I
Contents II
List of Figure IV
List of Tables V
Chapter 1 1
Introduction 1
Chapter 2 4
Related Work 4
2.1 Related Work 4
2.1.1 Software Enhancing Approach 4
2.1.2 Hardware Enhancing Approach 4
2.1.3 ASIC Encoding Approach 5
2.1.4 ASIP Encoding Approach 5
2.2 Motivation 6
Chapter 3 7
Design Specification, Design Flow, and Development Platform 7
3.1 Design Specification 7
3.2 Development Platform 8
3.3 Design Flow 9
Chapter 4 12
Proposed H.264 Video Encoder Architecture 12
4.1 Platform Frequency Concern 12
4.2 Block Diagram 12
4.3 Flexible Four-Stage Pipelined Architecture 14
4.4 Three-Level Main Controller 17
4.5 Memory Fetch Unit and Data Preloading 18
4.6 Memory Reuse in Inter Prediction 20
4.7 Direct Connection between IPs 21
Chapter 5 23
Software and System Consideration 23
5.1 Software Implementation 23
5.2 System-Level Memory Bandwidth Concern 24
5.3 System Communication and Integration 25
Chapter 6 27
Experiment Result 27
6.1 Design Statistic 27
6.2 Encoding Performance 29
6.3 Video Quality 30
6.4 Design Comparison 30
Chapter 7 32
Conclusion and Future Work 32
Bibliography 33
[1] AMBA Specification (Rev 2.0), ARM Ltd., Available: http://www.arm.com/products/solutions/AMBAHomePage.html
[2] C. C. Cheng, T. S. Chang, “Fast Three Step Intra Prediction Algorithm for 4x4 blocks in H.264,” IEEE International Symposium on Circuits and Systems (ISCAS 2005)
[3] C. R. Chang, “An IP-based Prototype for H.264 Decoding,” Master Thesis, National Tsing Hua University, Hsinchu, Taiwan, June 2005
[4] C. Y. Kao, H. C. Kuo, Y. L. Lin “High Performance Fractional Motion Estimation and Mode Decision for H.264/AVC”, International Conference on Multimedia & Expo (ICME)
[5] “Draft ITU-T Recommendation and Final Draft International Standard of Joint Video Specification (ITU-T Rec. H.264|ISO/IEC 14496-10 AVC),” JVT-G050, May. 2003
[6] Global Unichip UMVP-2000, Global Unichip Corporation. Available: http://www.globalunichip.com/
[7] H. F. Ate and Y. Altunbasak, “SAD Reuse In Hierarchical Motion Estimation For the H.264 Encoder”, IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP 2005)
[8] H. C. Kuo, “Efficient VLSI Architectures for Inter and Intra Mode Decision in High Resolution H.264/MPEG-4 Part10 AVC Encoding”, Master Thesis, National Tsing Hua University, Hsinchu, Taiwan, June 2006
[9] H. C. Tseng, “A Hardware Accelerator for H.264 Advanced Video Coding Motion Compensation”, Master Thesis, National Tsing Hua University, Hsinchu, Taiwan, June 2005
[10] International Electrotechnical Commission (IEC), http://www.iec.ch/index.html
[11] “Information Technology -Coding of Audio-Visual Objects -- Part 2: Visual (ISO/IEC 14496-2)”, ISO/IEC JTC1/SC29, 2004
[12] “Information Technology –Coding of Moving Picture and Associated Audio for Digital Storage Media up to 1.5Mbits/s, Part 2-Video (ISO/IEC 11172-2)”, ISO/IEC JTC1/SC29, June 1996
[13] “Information Technology -Generic Coding of Moving Pictures and Associated Audio Information: Video (ISO/IEC 13818-2)”, ISO/IEC JTC1/SC29, 2000
[14] International Organization for Standardization (ISO),
http://www.iso.org/iso/en/ISOOnline.frontpage
[15] International Telecommunication Union Telecommunication Standardization Sector (ITU-T), http://www.itu.int/ITU-T/
[16] JVT H.264/AVC Reference Software JM 9.0
[17] P. S. Liu, “A Hardware Context-Based Adaptive Binary Arithmetic Encoder for H.264 Advanced Video Coding” , Master Thesis, National Tsing Hua University, Hsinchu, Taiwan, June 2006
[18] S. López, F. Tobajas, A. Villar, V. de Armas, J. Fco. L. & R. Sarmiento, “Low Cost Efficient Architecture for H.264 Motion Estimation,” IEEE International Symposium on Circuits and Systems (ISCAS 2005)
[19] S. D. Kim, J. H. Lee, C. J. Hyun and M. H. Sunwoo, “ASIP Approach for Implementation of H.264/AVC”, IEEE International Symposium on Circuits and Systems (ISCAS 2006)
[20] S. Y. Shih, C. C. Chang, Y. L. Lin, “An AMBA-Compliant Deblocking Filter IP for H.264/AVC”, 2005 IEEE International Symposium on Circuits and Systems, page 4529-4532
[21] S. Y. Shih, “A High Performance Deblocking Filter for H.264 Advanced Video Coding”, Master Thesis, National Tsing Hua University, Hsinchu, Taiwan, June 2005
[22] T. C. Chen, C. J. Lian, and L. G. Chen, “Hardware Architecture Design of an H.264/AVC Video Codec”, IEEE International Symposium on Circuits and Systems (ISCAS 2006)
[23] Y. C. Kao, H. C. Kuo, Y. T. Lin, C. W. Hou, Y. H. Li, H. T. Huang, Y. L. Lin “A High-Performance VLSI Architecture for Intra Prediction and Mode Decision in H.264/AVC Video Encoding”, IEEE Asia Pacific Conference of Circuits and Systems
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