臺灣博碩士論文加值系統

隨著可攜式電子產品的快速發展，例如：手機、數位照相機等等；電源管理已經變得越來越重要與關鍵，並且朝著減少功率消耗發展。低壓降穩壓器大量的用在電源管理上，因為相較於切換式的穩壓器有著較好的暫態響應、較小的雜訊與較少的外接元件。但是低壓降穩壓器的穩定度會與準確度、暫態響應、調節度和所使用的外部元件等等，有所衝突。
這篇論文提出了兩個新的低壓降穩壓器。首先，一個使用電壓控制電流源當作微分器的無需外部電容的低壓降穩壓器被提出。傳統的低壓降穩壓器必須要有外部的電容提供濾波與穩定整個系統並且當負載改變時可降低輸出電壓的突然改變。因此所提出的低壓降穩壓器可適用於系統晶片(SOC)的應用與著重於輕薄短小的可攜式電子產品。所提出的第二個低壓降穩壓器是根據有電壓追隨器的米勒頻率補償法。它有快速的暫態反應、線調節度與負載調節度。
所有的實現的電路都是使用台積電的0.35微米互補式金氧半電晶體製程。頻率響應的迴路增益數學分析、設計議題與電路上的實現將會有深入

With the exponentially increasing of portable battery-powered electronic equipments, such as mobile phones, digital cameras and so on, power management has becoming more and more critical and focus on reducing the power consumption. Low dropout (LDO) regulators is widely used in power management since it has a better load transient response, less output noise and few off-chip components compared to switch-mode regulators. However, there are some tradeoffs among stability, accuracy, transient response, regulation and off-chip components, etc.
Two new architectures of LDO regulator are proposed in this thesis. First, the novel capacitor-free1 LDO regulator with voltage-controlled current source as a differentiator to increase the transient response is proposed. The conventional LDO regulator has to put the filtering capacitors at the output to ensure the stability and to reduce the voltage dip when load current changes. Therefore, the proposed LDO regulator is suitable for the System-on-Chip (SOC) applications and portable devices that need to reduce the volume and weight. Besides, the second proposed architecture of LDO regulator is based on the Miller compensation with voltage follower. It has the feature of fast transient response and good at both of line regulation and load regulation.
All the circuits are implemented in TSMC .35 CMOS process. The mathematical analysis of loop-gain of frequency response, design issues and circuit implements are addressed in detail.

Chapter1 Introduction 1
1.1 Background……………………………………………………………… 1
1.2 Motivation ………………………………………………………………. 2
1.3 Thesis Organization…………………………………............................... 2

Chapter2 Fundamentals of Low Dropout Regulators 4
2.1 Introduction to LDOs………………………………………………… 4
2.2 Specifications and Definitions of LDOs……………………………... 7
2.2.1 Input Voltage Range and Dropout Voltage ……………………. 8
2.2.2 Quiescent Current and Maximum Output Current…………….. 8
2.2.3 Power Efficiency………………………………………………. 9
2.2.4 Load Regulation……………………………………………….. 10
2.2.5 Line Regulation………………………………………………10
2.2.6 Temperature Coefficient ……………………………………….12
2.2.6 Power Supply Rejection Ratio…………………………………12
2.2.7 Noise……………………………………………………………15
2.2.7 Accuracy………………………………………………………..16
2.2.8 Load Capacitor and Its ESR…………………………………….14
2.3 System Design Considerations………………………………………..17
2.3.1 Transient Response…………………………………………….17
2.3.2 Frequency Response and Stability Issue………………………20
2.4 Summary………………………………………………………………24

Chapter3 Capacitor-Free CMOS Low Dropout Regulators with
Voltage-Controlled Current Source Compensation 25
3.1 Motivation…………………………………………………………….25
3.2 Architecture…………………………………………………………..27
3.3 Circuit Design and Simulation Results………………………………30
3.3.1 Circuit Design ………………………………………………..30
3.3.2 Frequency Response………………………………………….44
3.3.3 Simulation Results……………………………………………51
3.3.4 Layout………………………………………………………...55
3.4 Experimental Results……………………………………………………56
3.4.1 Test Setup…………………………………………………….56
3.5 Summary…………………………………………………………….57

Chapter4 Fast Settling CMOS Low Dropout Regulators with Source Follower Compensation 59
4.1 Motivation…………………………………………………………….59
4.2 Architecture…………………………………………………………...61
4.3 Circuit Design and Simulation Results……………………………….62
4.3.1 Circuit Design…………………………………………………62
4.3.2 Frequency Response…………………………………….65
4.3.3 Simulation Results…………………………………………….70
4.4 Summary……………………………………………………………...75

Chapter5 Conclusion and Future Work 77
5.1 Conclusion…………………………………………………………….77
5.2 Future Work……………………………………………………………

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