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研究生:李育陞
研究生(外文):Yu-Sheng Lee
論文名稱:IEEE1451.3網路媒體存取控制之設計與實現
論文名稱(外文):The Design and Implementation of IEEE1451.3 MAC
指導教授:許雅三
指導教授(外文):Yarsun Hsu
學位類別:碩士
校院名稱:國立清華大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2005
畢業學年度:94
語文別:英文
論文頁數:51
中文關鍵詞:感測器媒體存取控制層介面載波感測多重存取碰撞偵測錯誤偵測網路
外文關鍵詞:SensorMACInterfaceCSMA/CDError detectionNetwork
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近幾年來,感測器常常被用於提供像測量參數或者辨識操作狀態這類的資訊。雖然當今感測器已經被廣泛的使用了,然而它們始終缺乏一個共同的介面將它們整合起來。因此,為了製造具有統一介面而且低成本的智慧型感測器,IEEE 1451.3這個規範提供了一個非常適合的解決之道。IEEE 1451.3這個規範它藉著制訂一個共同的介面給多分支系統(multi-drop systems),以用來減輕製造廠商對於支援不同網路環境的感測器產品的負擔。

在這篇論文中,設計並且實現了IEEE 1451.3媒體存取控制層的部分,其中所實現的功能包括了包裝訊框、比對媒體存取控制(Media Access Control)位址以及錯誤偵測。除此之外,還加入了載波感測多重存取碰撞偵測(CSMA/CD)協定這種應用於解決網路上碰撞問題的協定。然而,在實作符合IEEE1451.3格式的媒體存取控制晶片時,除了要將上述的功能實現出來之外,另外特別要注意的是IEEE 1451.3媒體存取控制晶片通常是應用在感測器的領域。因此,像電源的消耗以及面積的大小往往是很關鍵的因素。因為一個感測器如果有著較低的電源消耗,意味著有較長時間的續航力,也就更具有實用的價值了。所以在設計的時候,需要考慮到媒體存取控制(MAC)架構對於電源消耗以及面積大小的影響。最後,這個設計是以國家晶片中心所提供的UMC 0.18微米的元件庫來合成的,所實現的電路其邏輯閘的數目約6.3k個,而在電源消耗的部分則是大約是570微瓦。
In recent year, sensors are used to provide information about the measured parameters or to identify control states. Although they are widely used by diverse applications nowadays, they still cannot be easily integrated due to the lack of a set of common interfaces. To build unified, low-cost and networked smart sensors, IEEE 1451.3 is a very feasible solution. It provides a common interface for distributed multi-drop systems, which can relieve the burden of the manufacturer for supporting a cross product of sensors versus networks.

In this thesis, I design and implement IEEE 1451.3 MAC layer into a chip. The implementation includes IEEE 1451.3 MAC (Media Access Control) functions, such as framing/deframing, addressing, and error detection. In addition, I also realize a CSMA/CD (Carrier Sense Multiple Access/Collision Detection) scheme used to resolve the collision problem in the sensor network. All of these functions are synthesized with UMC advanced 0.18um cell library provided by CIC. Since the goal of this design is to implement an IEEE 1451.3 MAC chip which is suitable for applications in sensor nodes, issues such as power consumption and area cost are most important. The one with lower power consumption is the one with the long life time, which in turn is of greater worth. To meet this requirement, the power consumption and gate counts must be taken into consideration carefully. In this design, the total gate counts of the circuit are about 6.3k with the power consumption about 570uW.
Content


List of Figures vi
List of Tables viii
1 Introduction 1
1.1 Overview of IEEE 1451.3 . . . . . . . .1
1.2 Motivation and objective . . . . . . . 4
1.3 Organization of this thesis . . . . . .5
2 Background 6
2.1 Introduction of IEEE1451.3 MAC . . . . 6
2.2 Main functions of IEEE1451.3 . . . . . 8
2.3 Elements of the IEEE 1451.3 MAC frame .8
2.4 Short format link control frame . . . .15
2.5 Error detection. . . . . . . . . . . . 17
3 Design and Implementation 12
3.1 Global design . . . . . . . . . . . . .19
3.2 Interface description. . . . . . . . . 22
3.3 MAC_TX structure . . . . . . . . . . . 25
3.4 MAC_RX structure . . . . . . . . . . . 30
3.5 CRC generator . . . . . . . . . . . . .34
4 Experimental Results 38
4.1 Design Environment. . . . . . . . . . .38
4.2 Simulation results. . . . . . . . . . .40
4.3 Synthesis report . . . . . . . . . . . 46
5 Conclusion and future work 47
5.1 Conclusion . . . . . . . . . . . . . . 47
5.2 Future work . . . . . . . . . . . . . .49
Bibliography 50






List of Figures


1.1 Physical context for IEEE 1451.3 . . . . 3
1.2 Model of the protocol stack . . . . . . .4

2.1 MAC Frame . . . . . . . . . . . . . . . .9
2.2 Frame control field order . . . . . . . .10
2.3 Data scrambler . . . . . . . . . . . . . 12
2.4 MAC address format . . . . . . . . . . . 13
2.5 A bit wide CRC generator . . . . . . . . 18

3.1 Global design structure. . . . . . . . . 20
3.2 MAC interface signals . . . . . . . . . .23
3.3 MAC_TX structure . . . . . . . . . . . . 26
3.4 TX_MAIN state machine . . . . . . .. . . 27
3.5 MAC_RX structure . . . . . . . . . . . . 31
3.6 MAC_RX state machine . . . . . . . . . . 32
3.7 CRC-32 implementation . . . . . . . . . .36
3.8 CRC-16 implementation . . . . . . . . . .37

4.1 Cell-based design flow chart. . . . . . .39
4.2 Carrier is sensed . . . . . . . . . . . .40
4.3 No carrier is sensed. . . . . . . . . . .41
4.4 Collision is detected . . . . . . . . . .41
4.5 TX starts. . . . . . . . . . . . . . . . 42
4.6 TX CRC. . . . . . . . . . . . . . . . . .43
4.7 RX CRC32. . . . . . . . . . . . . . . . .43
4.8 RX CRC16. . . . . . . . . . . . . . . . .44
4.9 RX address checking step1. . . . . . . . 45
4.10 RX address checking step2 . . . . . . . .45






List of Tables


Table 2.1 Status bits. . . . . . . . . . . . .7
Table 2.2 Frame control field. . . . . . . . .10
Table 2.3 Payload encoding. . . . . . . . . . 12
Table 2.4 short format link control frame. . .16
Table 2.5 Short format field definitions. . . 16

Table 3.1 (a) MAC global signals . . . . . . .22
(b) MAC interface signals . . . . . 22
Table 3.2 TX_MAIN state machine description. .28
Table 3.3 RX_MAIN state machine description. .33

Table 4.1 Synthesis power report. . . . . . . 46
Table 4.2 Synthesis area report. . . . . . . .46

Table 5.1 MAC comparison . . . . . . . . . . .49
[1] IEEE Std 1451.3-2003, IEEE Standard for a Smart Transducer Interface for Sensors and Actuators-Digital Communication and Transducer Electronic Data Sheet (TEDS) Formats for Distributed Multidrop Systems.

[2] IEEE Std 1451.1-1999, IEEE Standard for a Smart Transducer Interface for Sensors and Actuators—Network Capable Application Processor (NCAP) Information Model.

[3] ISO/IEC 7498-1:1994 [B3].

[4] Information Technology - Telecommunications and Information Exchange between Systems - Local and Metropolitan Area Networks - Specific Requirements. Part 3: Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications.

[5] ITU-T Recommendation G.989.1-2001, Phoneline Networking Transceivers - Foundation.

[6] ITU-T Recommendation G.989.2-2001, Phoneline Networking Transceivers - Payload Format and Link Layer Requirements.

[7] http://www.homepna.org/

[8] Rajesh Nair, Gerry Ryan and Farivar Farzaneh,“A Symbol Based Algorithm for Hardware Implementation of Cyclic Redundancy Check ( CRC )“, Bay NetWorks, INC.,Santa Clara, 95052, 1997.

[9] Ethernet Blue Book, Ethernet specifications from September, 1980.

[10] A.K. Pandeya, and T.J. Cassa, Parallel CRC Lets Many Lines Use One Circuit Computer Design, Sept. 1975.

[11] http://www.cic.org.tw

[12] C.J Chen, “Design and Implementation of 10 Gigabit Ethernet MAC”, Master Thesis, Dept. Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan, June 2004.
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