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研究生:顏佳禾
研究生(外文):Jia-He Yan
論文名稱:適用於無線都會網路通訊通道編解碼器之設計與實現
論文名稱(外文):Design and Implementation of a Channel Coder/Decoder for WiMAX Communications
指導教授:馬席彬
指導教授(外文):Hsi-Pin Ma
學位類別:碩士
校院名稱:國立清華大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2005
畢業學年度:94
語文別:中文
論文頁數:105
中文關鍵詞:通道編解碼器順向錯誤更正碼無線都會網路理德─所羅門碼摺積碼維特比解碼器
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順向錯誤更正碼 (FEC)廣泛的使用在無線通訊系統中,像廣播系統、行動通訊及無線區域網路等。FEC主要被使用來降低位元錯誤機率 (BER)並提高傳送資料的品質。 FEC主要分成兩部分:第一部分是里德─所羅門碼 (RS code),主要用來更正隨機連續錯誤,而另一部分是摺積碼 (Convolutional code),主要用來更正隨機位元錯誤,除了順向錯誤更正碼外,連接在摺積編碼器和調變器之間的是位元交錯器,位元交錯器主要用來防止摺積碼接收到連續的錯誤訊號並增加摺積碼的錯誤更正能力。在本篇論文中提出了一個低複雜度、高效能的里德─所羅門解碼器及適用在不同通訊標準之可變限制長度的維特比解碼器 (Viterbi decoder)。

本論文所提出的里德─所羅門編解碼器是使用平行處理的錯誤症狀計算及佛尼演算法,平行處理可以提升RS解碼器的工作頻率。我們也找到了可分離式非規則性的有限場乘法器來實現乘加器並可以降低RS解碼器的面積複雜度,最後,我們使用無除法器之Berlekamp-Massey演算法 (Inversion free Berlekamp-Massey algorithm)來實現關鍵方程式解決器,使用此種演算法可以降低關鍵方程式解決器的複雜度。

本論文所提出的維特比解碼器是增加一個額外的模組─分支計量與路徑計量間的繞線產生器 (BARG)模組,增加這個模組可以提高維特比解碼器的利用性,而且只需要花費16週期即可完成BARG模組的初始化,因此降低了BARG模組的延遲,另ㄧ個特點為使用加法、比較及選擇器 (ACS)間的分享處理,本論文只使用限制長度為7的維特比解碼器來實現限制長度最高為9的維特比解碼器。

最後,我們使用Xilinx Spartan3的實驗板來實現我們提出的順向錯誤更正碼,此更正碼包括一個高效能的RS解碼器、一個可以規劃限制長度的維特比解碼器及解交錯器,在場可程式閘陣列 (FPGA)實現中,所提出的RS解碼器可以操作在150MHz、可規劃式維特比解碼器可以操作在20MHz。
Forward error correction (FEC) is widely used in wireless communication system, such like broadcast system, mobile communication and WLAN. FEC is used to reduce bit error rate (BER) and improve data quality. There are two code types for FEC design, the first type of FEC is the Reed-Solomon code, whose errors correct capability for both random and burst errors, and the other type is the convolutional code, whose error correct capability for both random bit errors. In addition, between the convolutional encoder and the modulator is a bit interleaver, which protects the convolutional code from severe impact of burst errors and increase overall coding performance. We design a low hardware complexity and high performance Reed-Solomon decoder and reconfigurable Viterbi decoder with different constraint length for multi-standard communications in this thesis.

The proposed RS codec processor uses parallel processing to implement syndrome computation and Forney algorithm. Parallel processing improves the operation frequency of RS decoder. We also find the some implementation of finite field multiplier to reduce the area complexity, and choose inversion-free Berlekamp-Massey algorithm for key-equation solver because of the designed concern about hardware complexity decreasing.

The proposed reconfigurable Viterbi decoder adds the extra BARG module to improve the flexibility of hardware usage. It only needs 16 cycles to initialize BARG operation, so we can reduce the latency of BARG module. And other feature is we use sharing processing to implement the numbers of constraint length is nine based on Viterbi decoder with constraint length is seven.

At finally, we used a Xilinx Spartan3 development board to implement a proposed FEC with a high performance RS decoder, a reconfigurable Viterbi decoder and de-interleaver. The proposed RS decoder can operate at 150MHz; the proposed reconfigurable Viterbi decoder can operate at 20MHz for FPGA implementation.
1 Introduction 1
1.1 Background 1
1.2 Motivation 2
1.3 Organization of the Thesis 3

2 FEC Codec Overview for 802.16-2004 5
2.1 Reed-Solomon Encoder/Decoder 6
2.1.1 Finite Field GF(2m) 6
2.1.2 Encoding of Reed-Solomon Code 7
2.1.3 Decoding of Reed-Solomon Code 9
2.1.3.1 Algebraic decoding algorithm 9
2.1.3.2 Berlekamp-Massey algorithm 14
2.1.3.3 Inverse-free Berlekamp-Massey algorithm 16
2.1.3.4 Euclidean algorithm 17
2.2 Convolutional code and Viterbi algorithm 18
2.2.1 Introduction of convolutional code 18
2.2.2 Introduction of Viterbi algorithm 21
2.3 Interleaver 26

3 FEC Codec Architecture for 802.16-2004 29
3.1 Reed Solomon decoder architecture 29
3.1.1 Syndrome computation 30
3.1.2 Key equation solver 31
3.1.3 Error evaluation polynomial generator 36
3.1.4 Chien searcher and Forney processor 37
3.2 Viterbi decoder architecture 40
3.2.1 Hard decision and soft decision 41
3.2.2 Implementation issues of ACSU 43
3.2.3 The survivor memory management unit (SMU) 51
3.2 Interleaver and de-interleaver architecture 52

4 Proposed FEC Codec for 802.16-2004 55
4.1 Proposed Reed-Solomon codec 56
4.1.1 The finite field multiplier 56
4.1.2 The propose RS decoder 61
4.1.2 Comparison 70
4.2 Reconfigurable Viterbi decoder 71
4.2.1 The fixed state reconfigurable Viterbi decoder 71
4.2.2 ACSU sharing 80
4.2.3 Survivor memory unit 83
4.2.4 Comparison 85

5 Simulation and Implementation 87
5.1 System Simulation 87
5.2 SystemC and Verilog Simulation 92
5.3 FPGA Implementation 94

6 Future Works and Conclusions 99
6.1 Future Works 99
6.2 Conclusions 100

Bibliography 103
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[21] G.. Feygin and P. G. Gulak, “Architectural Tradeoffs for Survivor Sequence Memory Management in Viterbi Decoders,” IEEE Trans. Communications, Vol. 41, pp. 425-429, March 1993.
[22] L. Song and K. K. Parhi, “Low-Complexity Modified Mastrovito Multipliers over Finite Fields GF(2m),” IEEE Proc. Circuits and Systems, Vol. 1, pp. 508-512, June 1999.
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