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[1] L. JD and S. JJ, “An experimental delay test generator for lsi logic,” in IEEE Transactions on Computer, vol. 29, no. 3, March 1980, pp. 235–248. [2] M. Sharma and J. H. Patel, “Bounding circuit delay by testing a very small subset of paths,”in Proceedings of IEEE VLSI Test Symposium, April 2000, pp. 333–341. [3] A. Krstic and K.-T. Cheng, Delay Fault Testing for VLSI Circuit. Boston, MA: Kluwer Academic Publishers, 1998. [4] G. L. Smith, “Model for delay faults based upon paths,” in Proceedings of IEEE International Test Conference, November 1985, pp. 342–349. [5] W. N. Li, S. M. Reddy, and S. K. Sahni,“On path selection in combinational logic circuits,”in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 8, no. 1, January 1989, pp. 56-63. [6] A. K. Majhi, J. Jacob, L. M. Patnaik, and V. D. Agrawal, “On test coverage of path delay faults,” in Proceedings of 9th International Conference on VLSI Design, January 1996, pp. 418–421. [7] Y. K. Malaiya and R. Narayanaswamy, “Modeling and testing for timing faults in synchoronous sequential circuits,” in Design & Test of Computers, vol. 1, no. 4, November 1984, pp. 62–74. [8] K. Fuchs, F. Fink, and M. H. Schulz, “Dynamite: An efficient automatic test pattern generation system for path delay faults,” in IEEE Trans. on CAD, vol. 10, October 1991, pp. 1323–1335. [9] I. Pomeranz, S. M. Reddy, and P. Uppaluri, “A non-enumerative test generation method for path delay faults in combinational circuits,” in Proc. 30th Design Automation Conf., June 1993, pp. 439–445. [10] E. S. Park, B. Underwood, T. W. Williams, and M. R. Mercer, “Delay testing quality in timing-optimized designs,” in Proceedings of IEEE International Test Conference, October 1991, pp. 897–905. [11] C. J. Lin and S. M. Reddy, “On delay fault testing in logic circuits,” in IEEE Transactions on Computer-Aided Design of Integrated Circuit and Systems, vol. 6, no. 5, September 1987, pp. 694–703. [12] K. T. Cheng. and H. C. Chen, “Classification and identification of nonrobust untestable path delay faults,” in IEEE Transactions on Computer-Aided Design of Integrated Circuit and Systems, vol. 15, no. 8, August 1996, pp. 845–853. [13] M. A. Gharaybeh, M. l. Bysgbekk, and V. D. Agrawal, “Classification and modeling of path delay faults and test generation using single stuck-fault tests,” in Proceedings of IEEE International Test Conference, October 1995, pp. 139–148. [14] W. K. Lam, A. Saldanha, R. K. Brayton, and A. L. Sangiovanni-Vicentelli, “Delay fault coverate, test set size , and performance trade-offs,” in IEEE Transactions on Computer-Aided Design of Integrated Circuit and Systems, vol. 14, no. 1, January 1995, pp. 32–44. [15] U. Sparmann, D. Luxenburger, K. T. Cheng, and S. M. Reddy, “Fast identification of robust dependent path delay faults,” in Proceedings of 32nd Design Automation Conference, June 1995, pp. 119–125. [16] K. Fuchs, F. Fink, and M. H. Schulz, “Dynamite: An efficient automatic test pattern generation system for path delay faults,” in IEEE Transactions on Computer-Aided Design of Integrated Circuit and Systems, vol. 10, October 1991, pp. 1323–1335. [17] G. MA, B. ML, and A. VD, “An exact non-enumerative fault simulatio for path-dealy faults,”in Proceedings International Test Conference, October 1996, pp. 276–285. [18] J. J. Liou, K. T. Cheng, and D. A. Mukherjee, “Path selection for delay testing of deep submicron devices using statistical performance sensitivity analysis,” in Proceedings of IEEE VLSI Test Symposium, April 2000, pp. 97–104. [19] J. J. Liou, K. A., L. C. Wang, and K. T. Cheng, “False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation,” in Design Automation Conf., June 2002, pp. 566–569. [20] J. J. Liou, K. A., Y. M. Jiang, and K. T. Cheng, “Modeling, testing, and analysis for delay defects and noise effect in deep submicron devices,” in IEEE Transactions on Computer-Aided Design of Integrated Circuit and Systems, June 2003, pp. 756–769.
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