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研究生:陳森龍
研究生(外文):Sel-Lung Chen
論文名稱:針對延遲錯誤之以硬體為基底之虛擬窮盡測試樣本產生器
論文名稱(外文):Hardware-based Pseudo-exhaustive Test Pattern Generation for Delay Faults
指導教授:劉靖家
指導教授(外文):Jing-Jia Liou
學位類別:碩士
校院名稱:國立清華大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2005
畢業學年度:94
語文別:中文
論文頁數:63
中文關鍵詞:內建式自我測試延遲錯誤線性迴授移位暫存器傳輸延遲錯誤測試
外文關鍵詞:BISTDelay faultLFSRTransition delay faultTesting
相關次數:
  • 被引用被引用:0
  • 點閱點閱:234
  • 評分評分:
  • 下載下載:10
  • 收藏至我的研究室書目清單書目收藏:0
近年來,隨著晶片內的電晶體數目急遽增加;因此電路的運作頻率相形之下也變得比過往快很多。如此一來,就衍生出如何測試這些頻率很快的電路之問題。內建式自我測試之重要性相形之下也越發明顯,因為此一方法是透過內建測試電路在晶片中;如此一來,即可解決自動測試機器之頻率遠慢於電路之問題。另外一個問題是與時間相關之錯誤的嚴重性,此一類型之錯誤稱之為延遲錯誤。在最近幾年中,有一些針對將內建式自我測試應用在延遲錯誤偵測上之研究;然而,利用內建式自我測試測量延遲錯誤此一方法目前尚存在著一些問題,例如:測試樣本的產生、過度測試之問題與將測試樣本內嵌至硬體中等等。
在本篇論文中,我們想要以最少之硬體消耗產生所有利用以滿足為基底(SAT-based)之自動樣本產生器所產生之決策性延遲錯誤測試樣本。我們提出了一個方法(Heuristic)來解決此一問題,並與最佳化解之窮盡搜尋法(Exhaustive search)做一比較。另外,我們利用可變型態之線性回授移位暫存器(Reconfigurable LFSR)取代一般傳統之線性回授移位暫存器。最後,我們列舉一些針對傳輸錯誤測試樣本與路徑錯誤測試樣本使用所提出之方法所得到之結果,以及在最後我們歸結出一些簡單的結論。
Recently years, the clock frequency of chips is more faster than before. There are some problems of testing those faster chips. BIST approach is more important because it embedded the test hardware into chips. Therefore, it can solve the problem of speed of ATE is much slower
than circuits. The other problem is that the time-related faults,i.e, delay faults. However, there are still some problem of BIST and delay fault
testings.
In this thesis, we want to generate all deterministic delay fault test patterns which are generated by SAT-based ATPG tool with minimum hardware cost. We propose a heuristic to achieve this objective. We use the reconfigurable LFSR instead of generic LFSR. Finally, we show the experimental result of SAT-based ATPG and use heuristic for transition fault test patterns and path delay fault test patterns.
1 Introduction 1
1.1 Background of Built-in Self Test . . . . . . . . . . . . . . . 1
1.1.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1.2 Test Pattern Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.1.3 Response Analyzer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1.4 Test-Per-Clock and Test-Per-Scan Configuration . . . . . . . . . . . . . . 5
1.2 Test Application Scheme for Delay Fault Testing . . . . . . . . . . . . . . . . . . 6
1.2.1 Combinational Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2.2 Sequential Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3 Transition Fault Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.4 Background of Path Delay Fault . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.4.1 Path Delay Fault Model . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.4.2 Path Delay Fault Classification . . . . . . . . . . . . . . . . . . . . . . . . 13
1.5 Why use BIST to test delay fault ? . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2 Previous Work 17
2.1 Previous Work of Built-in Self Test . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.2 Previous Work of Delay Fault BIST . . . . . . . . . . . . . . . . . . . . . . . . . 20
3 The Proposed Method 24
3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.2 Exhaustive Search and Heuristic . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.2.1 Exhaustive Search . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.2.2 Heuristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.3 Limitation of LFSR Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.4 Strategy of Changing LFSR Configuration . . . . . . . . . . . . . . . . . . . . . . 32
3.5 Including Fault Simulation with Processing . . . . . . . . . . . . . . . . . . . . . 33
3.6 Reconfigurable LFSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.7 Fixed the PI Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4 Experimental Results 37
4.1 SAT-based Transition Delay Fault ATPG and Fault Simulation . . . . . . . . . . . 37
4.2 Process with Path Delay Fault Test Pattern . . . . . . . . . . . . . . . . . . . . . . 38
4.3 ExperimentalResult of SAT-based ATPG Tool . . . . . . . . . . . . . . . . . . . . 39
4.4 Experimental Result of Heuristic . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.4.1 Exhaustive Search versus Heuristic . . . . . . . . . . . . . . . . . . . . . 42
4.4.2 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.4.3 Transition Delay Fault Test Patterns . . . . . . . . . . . . . . . . . . . . . 44
4.4.4 Fix PI Transition Fault Test Patterns . . . . . . . . . . . . . . . . . . . . . 45
4.4.5 Path Delay Fault Test Patterns . . . . . . . . . . . . . . . . . . . . . . . . 48
5 Conclusions and Future Work 57
5.1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
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