臺灣博碩士論文加值系統

時間訊號偏移(Jitter)於目前的電子系統裡是種極為不好的現象，所以一般在規格表上都會有對於時間偏移的程度做嚴謹的規範。由於製程的進步，時脈頻率操作於GHZ的速度之上，時間偏移(jitter)成為電子系統上的效能限制，所以我們對於時間偏移的要求越來越有嚴格的要求。傳統上的量測時脈誤差是由外接儀器來測量，但隨著製程的進步時間偏移越來越小甚至到了微微秒(picosecond)。能精確到微微秒的量測儀器卻是極為昂貴的，花費過高時間冗長且精確度容易受探針或周邊雜訊的影響導致不精確。所以Built In Self Test(BIST)是現今的趨勢。鎖相迴路(PLLs)常用於合成頻率及時脈產生於電子系統中，所以對於其時間偏移的規格甚為嚴謹，故此論文針對PLL做時間偏移的量測電路。
此篇論文以內嵌式電路量測時派產生的偏移，以精確，省錢，省時的方式量測鎖相迴路的時間偏移誤差。此電路有兩種模式，一為平均的時間偏移誤差另一為警告模式。平均模式則是計算連續序列的時脈訊號求取其平均值可藉此了解其平均的分布區域。警告模式則是假設規格表規定此處的時脈訊號偏移不得超越某個特定的值，一旦此時脈訊號超過此值，此電路會發出訊號告知使用著此PLL已經不符合規格表的規範。此電路可有效減小量測時間及提高精確度且不會佔據太大的面積。經由HSPICE在0.18um製程之下模擬，可得其平均模式的誤差約為8％。

This thesis presents an on-chip phase-locked loops (PLLs) jitter timing measurement design that the expected deviation from the specification and the average jitters can be measured. Examining the measured signals whether they conform to the specification, the proposed circuit is operated at every cycle of the PLL’s reference frequency without using an extra sampling clock and provides a robust result and low area overhead. A series of pulses with average length of 100-ps is injected in the proposed circuit, and the test results show about 8% measurement errors.
With lower area overhead, the proposed design can measure accumulated jitter and give a warning signal if a clock’s jitter over a specific value. To verify the correctness of the design, the proposed circuit is simulated by HSPICE in a standard 0.18-um CMOS technology.

Contents
Abstract 1
Contents 2
Chapter1 6
Introduction 6
1.1 Conventional PLLs operation 8
1.2 Jitter Source 9
1.3 Jitter Definition 11
1.4 Summary 14
Chapter2 15
Previous Works 15
2.1 Thermometer Code Method 15
2.2 Time-to-Voltage Converter Based Method 17
2.3 Vernier Delay Line Based Method 18
2.4 Self Reference, Vernier Delay Line Based Method 20
2.5 Summary 23
Chapter3 24
Proposed Work 24
3.1 Basic Concept 24
3.2 Proposed Circuit 28
3.3 Average Mode 29
3.4 Warning Indicator Check 35
3.5 Simulation Result 37
3.6 Comparisons 41
3.7 Summary 42
Chapter4. 43
Conclusions 43
Bibliography 44

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