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研究生:陳江陽
研究生(外文):Chen, Jiang-Yang
論文名稱:串流加解密FPGA實作
論文名稱(外文):The FPGA Implementation of a Stream Cipher
指導教授:詹景裕詹景裕引用關係
指導教授(外文):Jan, Gene-Eu
學位類別:碩士
校院名稱:國立臺北大學
系所名稱:通訊工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2006
畢業學年度:94
語文別:中文
論文頁數:29
中文關鍵詞:可程式陣列閘串流加密密鑰流產生器
外文關鍵詞:field programmable fate arraystream cipherkey generator
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由於電腦與網路的應用日漸普及,資訊的安全與完整比以往更重要。因為對語音與影像的需求,帶動手機與網際網路的高速傳輸,在實用上需考量安全性與即時性,區塊密碼雖然安全但是無法滿足即時性,串流密碼在即時性比區塊密碼有很好的表現。因此本文引用張仁俊等提出的架構配合可程式陣列閘(Field Programmable Gate Array,FPGA)實作同步串流加解密系統中的密鑰流產生器(Key generator)。本密鑰流產生器由線性反饋移位暫存器(Linear feedback shift register,LFSR)、組合器(combination generator)與濾波器(Filter generator)所組成。實作部份以硬體描述語言Verilog撰寫,配合可程式陣列閘Stratix EP1S80 DSP完成硬體驗證功能。所需logic elements數量為259,在時脈頻率為184 MHz時下,鮑率可達184 Mbps。
Data encryption/decryption plays an important role in communication and network securities. The demand of multimedia promotes the high-speed transmission in the mobile phone and Internet. The block ciphers are safe but unable to meet the requirement of real-time process; therefore, stream ciphers are applied to the real-time system. In the thesis, we use field programmable gate array to implement the key generator of synchronous stream system. The key generator consists of linear feedback shift register, combination generator and filter generators. Our design is coded using Verilog HDL and implemented on Altera’s FPGA Stratix EP1S80 DSP. Our design requires 259 logic elements and achieves a data throughput up to 184 Mbps in a maximum clock frequency of 184 MHz.
1.緒論 1
2.串流密碼簡介 3
3.串流加解密設計 5
3.1線性反饋移位暫存器與過濾器模組 9
3.2 組合器模組 13
4.串流加解密之FPGA平台 15
4.1 Case I 16
4.2 Case II 16
4.3 Case III 16
4.4 Case IV 17
4.5 Case V 17
5硬體實作 18
6.效能分析 25
7.結論 26
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