臺灣博碩士論文加值系統

本論文中提出雙材料雙閘完全解離絕緣體上矽金氧半元件在直流與交流的分析。

第一章主要是針對SOI元件做一個簡介，說明SOI元件如何從bulk元件演化而來，並提出一個新型雙材料雙閘完全解離絕緣體上矽金氧半元件。

第二章則是探討通道長度為100奈米雙材料雙閘完全解離絕緣體上矽金氧半元件，當上閘極為N+多晶矽，下閘極分別是N+和P+多晶矽不同比例的混合和不同的薄膜摻雜濃度時，其直流現象的分析。

第三章則是探討通道長度為100奈米雙材料雙閘完全解離絕緣體上矽金氧半元件，當上閘極為N+多晶矽，下閘極分別是N+和P+多晶矽不同比例的混合和不同的薄膜摻雜濃度時，其電容現象的分析。

This thesis reports an analysis of DC and AC behavior of dual-material (DM) double-gate (DG) fully-depleted (FD) silicon on insulator (SOI) MOS device.

In chapter 1, we make an introduction for SOI device and describe its evolution from bulk device and propose a new structure called dual-material double-gate fully-depleted silicon on insulator MOS device.

In chapter 2, we discuss the DC phenomenon of a 100nm DMDG FD SOI MOS device with the N+ poly top gate and different ratio N+/P+ poly bottom gate and different thin film doping.

In chapter 3, we discuss the capacitance phenomenon of a 100nm DMDG FD SOI MOS device with the N+ poly top gate and different ratio N+/P+ poly bottom gate and different thin film doping.

1 導論 1
1-1 為什麼是SOI元件 1
1-2 部份解離 vs. 完全解離 2
1-3 SOI MOS元件 3
1-4 DG SOI MOS 元件 4
1-5 DG FD SOI MOS元件 5
1-6 DMDG FD SOI MOS元件 6
1-7 本篇論文的目標 7

2 通道長度100奈米雙材料雙閘完全解離絕緣體上矽金氧半元件，當上閘極為N+多晶矽，下閘極分別是N+和P+多晶矽不同比例的混合和不同的薄膜摻雜濃度時，其直流現象的分析 8
2-1 元件結構簡介 8
2-2 電流現象分析 10
2-3 電位現象分析 12
2-4 電場現象分析 15
2-5 改變薄膜濃度的比較 20
2-6 結論 26

3 通道長度100奈米雙閘完全解離絕緣體上矽金氧半元件，當上閘極為N+多晶矽，下閘極分別是N+和P+多晶矽不同比例的混合和不同的薄膜摻雜濃度時，其電容現象的分析 27
3-1 簡介 27
3-2 電容現象 28
3-3 電容行為的分析 30
3-4 等效電容模型 39
3-5 改變薄膜濃度的比較 43
3-6 結論 46

4 總結 47

參考文獻 48

第1章
[1] J. B. Kuo,”數位 IC”,全華, 2004.
[2] J. B. Kuo and S. C. Lin, Low-Voltage SOI CMOS VLSI Devices and Circuits. New York: Wiley, 2001.

第2章
[1] A new dual-material double-gate (DMDG) nanoscale SOI MOSFET-two-dimensional analytical modeling and simulation
Reddy, G.V.; Kumar, M.J.;Nanotechnology, IEEE Transactions on
Volume 4, Issue 2, March 2005 Page(s):260 – 268
[2] A new dual-material double-gate (DMDG) SOI MOSFET for nanoscale CMOS design
Reddy, G.V.; Kumar, M.J.;Semiconductor Device Research Symposium, 2003 International
10-12 Dec. 2003 Page(s):238 - 239

第3章
[1] Investigation of the novel attributes of a fully depleted dual-material gate SOI MOSFET
Chaudhry, A.; Kumar, M.J.; Electron Devices, IEEE Transactions on
Volume 51, Issue 9, Sept. 2004 Page(s):1463 - 1467.
[2] Exploring the novel characteristics of fully depleted dual-material gate (DMG) SOI MOSFET using two-dimensional numerical simulation studies
Chaudhry, A.; Kumar, M.J.;VLSI Design, 2004. Proceedings. 17th International Conference on
2004 Page(s):662 - 665.
[3] Two-dimensional analytical threshold voltage model for DMG Epi-MOSFET
Goel, K.; Saxena, M.; Gupta, M.; Gupta, R.S.;Electron Devices, IEEE Transactions on
Volume 52, Issue 1, Jan. 2005 Page(s):23 - 29.
[4] Analytical model for the threshold voltage of dual material gate (DMG) partially depleted SOI MOSFET and evidence for reduced short-channel effects
Kumar, M.J.; Reddy, G.V.;Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on
Volume 2, 18-21 Oct. 2004 Page(s):1204 - 1207 vol.2.
[5] Dual-material gate (DMG) field effect transistor
Long, W.; Ou, H.; Kuo, J.-M.; Chin, K.K.;Electron Devices, IEEE Transactions on
Volume 46, Issue 5, May 1999 Page(s):865 - 870.
[6] Physics-based analytical modeling of potential and electrical field distribution in dual material gate (DMG)-MOSFET for improved hot electron effect and carrier transport efficiency
Saxena, M.; Haldar, S.; Gupta, M.; Gupta, R.S.;Electron Devices, IEEE Transactions on
Volume 49, Issue 11, Nov. 2002 Page(s):1928 - 1938.
[7] Two-dimensional analytical modeling and simulation of the potential and threshold voltage of a new fully depleted dual metal gate SOI MESFET
Hashemi, P.; Behnam, A.; Fathi, E.; Afzali-Kusha, A.;Microelectronics, 2004. ICM 2004 Proceedings. The 16th International Conference on
6-8 Dec. 2004 Page(s):372 – 375.
[8] Two-dimensional analytical modeling of fully depleted DMG SOI MOSFET and evidence for diminished SCEs
Kumar, M.J.; Chaudhry, A.;Electron Devices, IEEE Transactions on
Volume 51, Issue 4, April 2004 Page(s):569 – 574.
[9] Controlling short-channel effects in deep-submicron SOI MOSFETs for improved reliability: a review
Chaudhry, A.; Kumar, M.J.;Device and Materials Reliability, IEEE Transactions on
Volume 4, Issue 1, March 2004 Page(s):99 – 109.
[10] A new dual-material double-gate (DMDG) nanoscale SOI MOSFET-two-dimensional analytical modeling and simulation
Reddy, G.V.; Kumar, M.J.;Nanotechnology, IEEE Transactions on
Volume 4, Issue 2, March 2005 Page(s):260 – 268
[11] A new dual-material double-gate (DMDG) SOI MOSFET for nanoscale CMOS design
Reddy, G.V.; Kumar, M.J.;Semiconductor Device Research Symposium, 2003 International
10-12 Dec. 2003 Page(s):238 - 239