臺灣博碩士論文加值系統

在本論文中，我們介紹了各種不同類別的功率放大器以及數種功率放大器的效率增進技術。更進一步，本論文設計與製作了數個以金氧半與矽鍺製程製作且供無線通訊應用的功率放大器。以0.18微米金氧半製程製作的自我偏壓串聯功率放大器，達成了15.3 dB的線性增益、18.8 dBm的飽和功率、17.7 dBm的1dB壓縮點以及25.6 %的功率增加效率；以0.35微米矽鍺製作的並聯多功率級功率放大器，在模擬上高功率級有28.7 dB的線性增益、28.9 dBm的飽和功率、26.6 dBm的1dB壓縮點以及41 %的1dB壓縮點增加效率，而低功率級則有27.5 dB的線性增益、22.3 dBm的飽和功率、21.8 dBm的1dB壓縮點以及31.6 %的1dB壓縮點增加效率；同樣以0.35微米矽鍺製作的具功率結合器功率放大器，達成了14 dB的線性增益、28.5 dBm的飽和功率、27.9 dBm的1dB壓縮點以及22.6 %的1dB壓縮點增加效率。此外，在本論文中我們也說明了這些不同架構的功率放大器各自的設計概念、設計流程與使用印刷電路版的量測方式。

In this thesis, some different classifications and efficiency enhancement techniques of power amplifiers are introduced. Furthermore, some CMOS and SiGe power amplifiers used for wireless communication applications are designed and fabricated. For 0.18μm self-biased cascade CMOS power amplifier, it achieves 15.3 dB linear gain, 18.8 dBm Psat, 17.7 dBm P1dB, and 25.6 % PAE@P1dB; For 0.35μm parallel multiple power-stages SiGe power amplifier, in simulation, it achieves 28.7 dB linear gain, 28.9 dBm Psat, 26.6 dBm P1dB, and 41 % PAE@P1dB in high power stage, and 27.5 dB linear gain, 22.3 dBm Psat, 21.8 dBm P1dB, and 31.6 % PAE@P1dB in low power stage; For 0.35μm SiGe power amplifier with power combiner, it achieves 14 dB linear gain, 28.5 dBm Psat, 27.9 dBm P1dB, and 22.6 % PAE@P1dB. In addition, each design concepts and flows of these power amplifiers with different structures and the measurement method with PCB module are described in this thesis.

Chapter 1 Introduction 1
1.1 Background 1
1.2 Motivation 2
1.3 Thesis Outline 3
Chapter 2 Classification of Power Amplifiers and Efficiency Enhancement Techniques 5
2.1 Introduction 5
2.2 Classification of Power Amplifiers 5
2.2.1 Linear Power Amplifiers 6
2.2.2 Non-Linear Power Amplifiers 8
2.2.2.1 Class D 8
2.2.2.2 Class E 10
2.2.2.3 Class F 11
2.3 PA Efficiency Enhancement Techniques 13
2.3.1 Doherty Amplifier 13
2.3.2 Chireix’s Outphasing Amplifier 16
2.3.3 Envelope Elimination and Restoration 17
2.3.4 Envelope Tracking 18
2.3.5 Multiple Power-Stage Power Amplifier 19
2.3.6 Power Combining 20
Chapter 3 2.4 GHz Self-Biased Cascode CMOS Power Amplifier 21
3.1 Introduction 21
3.2 Weaknesses of CMOS Technology 22
3.2.1 Low fmax 22
3.2.2 Low Breakdown Voltage 23
3.2.3 Low Substrate Resistivity 23
3.3 Theoretical Analysis and Circuit Design 24
3.3.1 Advantages of Self-Biased Cascode Topology 24
3.3.2 Other Circuit Blocks of Self-Biased Cascode CMOS PA 26
3.3.2.1 CMOS Transistors 26
3.3.2.2 Matching Circuits 27
3.3.2.3 λ/4 Transmission Line 28
3.3.3 Using Load-Line Theory to Optimize Biasing Point 28
3.3.4 Circuit Design Flow 31
3.4 Measurement 32
3.4.1 Measurement Method 32
3.4.2 Measurement Results 33
3.5 Discussion and Conclusion 35
Chapter 4 1.95 GHz SiGe Power Amplifier with Parallel Multiple Power Stages 36
4.1 Introduction 36
4.2 Theoretical Analysis and Circuit Design 36
4.2.1 Parallel Multiple Power-Stages Structure 37
4.2.2 Biasing Circuits with Temperature Compensation 39
4.2.3 Circuit Design Flow 40
4.3 Simulation and Measurement 40
4.3.1 Simulation Results 41
4.3.2 Measurement Results 43
4.4 Discussion and Conclusion 44
Chapter 5 1.95 GHz SiGe Power Amplifier with Power Combiner 46
5.1 Introduction 46
5.2 Advantages of Power Combining Technique with Lumped Component 46
5.2.1 Advantages of Power Combining Technique 47
5.2.1.1 The Loss of the Output Matching Circuit 47
5.2.1.2 The Limit of the Transistor Size 48
5.2.2 Advantages of Using Lumped Component 49
5.3 Theoretical Analysis and Circuit Design 49
5.3.1 Differential Power Combiner with Lumped Component 50
5.3.2 In-Phase Power Combiner with Lumped Component 52
5.3.3 Circuit Design Flow 52
5.4 Measurement 53
5.4.1 Measurement Method 54
5.4.2 Measurement Results 55
5.5 Discussion and Conclusion 58
Chapter 6 Summary and Future Work 59
6.1 Summary 59
6.2 Future Work 60
Reference 61

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