臺灣博碩士論文加值系統

近年來低功率的電子產品的需求是越來越重要，特別是應用於無線和感應器系統中•類比數位轉換器是此類系統中的重要原件，所以如何降低類比數位轉換器的耗電是一個熱門的研究題目•目前在感應器系統中主流的類比數位轉換器架構為電荷重新分佈式的循漸近式逼近法•在某些感應器應用裡需要一個較高解析度的類比數位轉換器•但是這架構的精準度通常只有到10位元其主要原因為電容之間的匹配誤差•加上校正電路後精準度是可以提高的，但是過去所提出的校正電路是很耗電的•本論文提出一個切換式電容的校正電路，可以提高精準度但是只耗少許的電•電荷重新分佈式的循漸近式逼近法轉換器架構於電荷守衡定律，電容陣列之間的匹配誤差會使在比較過程造成電壓的漂移•本校正電路基本的想法是在取樣的時候儲存固定的正或負電荷於校正電容裡，然後在比較過程中依據匹配誤差的量，把儲存的電荷在加進電容陣列中來校正電壓的漂移•本設計實現於TSMC 0.35μm CMOS的製程•晶片的面積為1.88x1.88mm2，類比數位轉換器核心面積為0.83 x 0.74mm2•轉換速度為每秒鐘20萬次•類比電路所量測到的耗電為1.35毫瓦在5伏特電工作電壓，數位電路所量測到的耗電為3.3毫瓦在3.3伏特電工作電壓•在動態精準度的量測值，自我校正前SNDR為63.9dB，SFDR為74.7dB•自我校正後SNDR為47.9dB，SFDR為50.6dB•在自我校正後準確度卻下降，這跟預期不同•其原因為測試電路上的吵雜環境•但是校正電路所影響的只有在單數諧的諧波，這跟理論推導是相同的•

The demand of low power electronic device is become strongly these years, especially in wireless and sensor network devices. Analog to digital converter (ADC) is the key building block of these devices. Therefore, a hot research topic is to reduce ADC power consumption. For some sensor application, the highly accuracy ADC is required. A main ADC architecture for sensor application is success approximation register (SAR). It’s accuracy is usually limited by the mismatch of capacitor array which is about 10 bit. A calibration circuit can be added to enhance the accuracy; however, it usually dissipates a lot power. This work presents a switch capacitor calibration technique to enhance the performance without consume a lot of power. The charge redistribution SAR ADC operation theory is base on charge conservation law. The mismatch of capacitor would cause the voltage shift during the comparison phase. The fundamental of this calibration idea is to store the positive and negative charge in the calibration capacitors during the sample phase. Then, during the comparison phase, these pre-stored charge injects into the main capacitor array to correct the voltage shift. This work is fabricated by TSMC 0.35um CMOS technology. The chip area is 1.88x1.88mm2, and the core area is 0.83 x 0.74mm2. The conversion rate is 200KS/s, and the measured analog power is 1.35mW at 5V and digital power is 3.3mW at 3.3V. The SNDR and SFDR before self-calibration are 63.9 and 74.7dB. After self-calibration process the SNDR and SFDR are 47.9 and 50.6dB. The performance after self calibration is degraded, and it is not expected. The cause of degrading may be noisily environment of testing board. However, the effect of this calibration circuit is only in odd harmonic, and it is the same as the prediction.

TABLE OF CONTENTS


摘要 I
Abstract II
Table of Contents IV
List of Figures VI
List of Tables IX

Chapter 1 INTRODUCTION 1
________________________________________
1.1 Motivation 1
1.2 Thesis Organization 2

Chapter 2 REVIEW OF SUCCESSIVE APPROXIMATION REGISTER A/D CONVERTER 3
________________________________________
2.1 Basic Theory 3
2.2 Charge Redistribution A/D Converter 5
2.3 Source of Error 11
2.3.1 Capacitor Mismatch 11
2.3.2 Operational Amplifier Gain Error and Offset 13
2.3.3 Aperture Jitter 14
2.3.4 Charge Injection and Clock Feedthrough 15
2.3.5 Leakage Current 16


Chapter 3 PROPOSE A NEW CALIBRATION METHOD 18
________________________________________
3.1 Passed Calibration Method 18
3.2 This Calibration Method 19
3.3 Steps of Self-Calibration 23

Chapter 4 CIRCUIT DESIGN 30
________________________________________
4.1 Overview 30
4.2 Digital Controller 31
4.3 Operation Amplifier 34
4.4 Self Calibration 36
4.5 Layout 37


Chapter 5 SIMULATION RESULT 40
________________________________________
5.1 Algorithm Simulation Result 40
5.2 Transistor Level Simulation Result 46

Chapter 6 MEASUREMENT RESULT 50
________________________________________
6.1 Measurement Setup 50
6.2 Performance without Calibration 53
6.3 Performance after Self-Calibration 55
6.4 Summary of Measurement Result 56

Chapter 7 CONCLUSIONS 58
________________________________________
7.1 Summary of Research Future Work 58
7.2 Summary of Research 59

BIBLIOGRAPHY 61
________________________________________

[1] David A. Johns, Ken Martin. ”Analog Integrated Circuit Design” John Wiley & Sons, Inc. 1997 Pages: 495
[2] Rudy van de Plassche “CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters” 2nd Edition, Kluwer Academic Publishers, 2003 Pages 103
[3] J. L. McCreary and P. R. Gray, “All-MOS charge redistribution analog-to-digital conversion techniques-Part I,” IEEE J. Solid-State Circuits, vol. SC-10, no. 6, pp. 371-379, Dec. 1975.
[4] R. Jacob Baker, Harry W. Li, David E. Boyce. “CMOS, Circuit Design, Layout, and Simulation” A John Wiley & Sons, Inc. and IEEE Press, 1997 Pages: 835
[5] Rudy van de Plassche “CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters” 2nd Edition, Kluwer Academic Publishers, 2003 Pages 521
[6] Hae-Seung Lee; Hodges, Dave A. “Self-calibration technique for A/D converters” Circuits and Systems, IEEE Transactions on , Volume: 30 , Issue: 3 , Mar 1983
Pages:188 – 190
[7] M. Shinagawa, Y. Akazawa, and T. Wakiomoto, “Jitter Analysis of High Speed Sampling Systems,” IEEE J. Solid-State Circuits, vol. SC-25, no. 2, pp. 220-224, Feb. 1990
[8] Behzad Razavi, “Principles of Data Conversion System Design” A John Wiley & Sons, Inc. and IEEE Press, 1995 Pages: 27
[9] Z. G. Boyacigiller, B. Weir, and P. D. Bradshaw, “An error-correcting 14b/20μs CMOS A/D converter,” 1981 IEEE Int. Solid Circuits Conf. Dig. of Technical Papers. Vol. XXIV. Pp. 62-63.
[10] K. Maio, M. Hotta, N. Yokozawa, M. Nagata, K. Kaneko, and T. Iwasaki, “An Untrimmed D/A Converter with 14-bit Resolution,” IEEE Trans. Solid-State Circuits. Vol. SC-16 Dec. 1981.
[11] Application Note 1040: http://www.maxim-ic.com/an1040, MAXIM INTEGRATED PRODUCTS, INC. Mar. 29, 2002
[12] Agilent 33250A 80 MHz Function/Arbitrary Waveform Generator, Service Guide, Agilent, Edition 2, March 2003, page 14.