臺灣博碩士論文加值系統

近年來，由於無線通訊的快速發展，加上半導體的日益成熟，促使現代化的無線產品需求，以及在消費市場主導下講究輕、薄、短、小以及低價位下，加速射頻積體電路(RFIC)的發展熱潮，如何利用CMOS製程提供更高度的整合便是現在的主要課題，藉由砷化鎵(GaAs)與CMOS的比較，進而了解製程的差異，以便進行改善。
本論文分為兩個部份，第一部分是以TSMC 0.18μm 1P6M CMOS 製程設計應用於802.11a之5.2GHz CMOS 接收機前端電路，在接收機的規劃上採取直接降頻式的接收機架構設計方式，設計出5.2GHz低雜訊放大器以及兩組降頻混波器，模擬結果低雜訊放大器增益為12.8dB、S11為-28.23dB、輸入P1dB為9.3dBm、IIP3為10.5dBm、雜訊指數為2.71dB，混波器方面轉換增益13.9dBm、SSB雜訊指數13.2dB、IIP3為5.2dBm。而第二部份則為製作一3-10GHz 超寬頻低雜訊放大器，低雜訊放大器的模擬增益在3-10GGHz頻段內約8-13dB，S11方面則皆小於-10dB，雜訊指數方面皆小於5dB，IIP3在6GHz的頻段為-7.5dBm，P1dB在6GHz的頻段則為-18.4dBm。

In recent years, with the rapid development of wireless communication as well as the maturation of semi-conductor technologies and industries, there is a substantial increase in customer demand for modern wireless products that are light, thin, short, small and low cost. The development of radio frequency integrated circuits is accelerated correspondingly. As the result, higher integration of CMOS process is now becoming a major issue. Through the comparison between GaAs and CMOS processes, we are able to understand their differences in nature and develop methodologies to deal with corresponding design problems.

The thesis is divided into two major parts. One is the design of an IEEE 802.11a CMOS 5.2GHz receiver front-end circuit in TSMC 0.18μm 1P6M CMOS process. The receiver is designed with direct conversion architecture which consists of a 5.2GHz LNA and two down conversion mixers. The simulation result of the LNA exhibits a gain of 12.8dB, a S11 of -28.23dB, an input P1dB of 9.3dBm, an IIP3 of 10.5dBm, and a NF of 2.71dB. The down conversion mixer exhibits a conversion gain of 13.9dBm, a SSB NF of 13.2dB and an IIP3 of 5.2dBm. The other is the development of a 3-10GHz UWB LNA. The simulation result of the UWB LNA shows a gain of 8-13dB, a S11 less than -10dB, a NF less than 5dB, an IIP3 -7.5dBm at 6GHz and a P1dB of -18.4dBm at 6GHz.

第一章 序論
第二章 射頻電路的設計考量
第四章 5.2GHz直接降頻式之低雜訊放大器及混波器設計
第五章 3.1-10.6GHz 超寬頻低雜訊放大器設計
第六章 總結討論與未來展

參考文獻


[1] IEEE Std 802.11a/D7.0-1999,”Part11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications: High-speed Physical Layer in the 5GHz Band.”
[2] ETSI,”Broadband Radio Access Networks (BRAN);HIPERLAN type 2 technical specification; Physical Layer(PHY),” Aug. 1999.
[3] Guillermo Gonzalez, “Microwave Transistor Amplifiers Analysis and Design,” 2nd Edition, Prentice-Hall, Inc. 1997.
[4] I.D. Robertson and S. Lucyszyn, “RFIC and MMIC Design and Technology,” Institution of Engineering and Technology, Aug. 1995.
[5] David M. Pozar, “Microwave Engineering“, 3rd Edition, John Wiley & Sons, Inc. 2005.
[6] B. Razavi, ”Design of Analog CMOS Integrated Circuits”, McGraw-Hill Education, 2000.
[7] K. Chang, I. Bahl and V. nair, “RF and Microwave Circuit and Component Design for Wireless System,” John Wiley & Sons, Inc. 2002.
[8] D. K. Shaeffer and T. H. Lee, “A 1.5-V, 1.5-GHz CMOS low noise amplifier,” IEEE JSSC., vol.32,No.5, pp.745-759, May 1997.
[9] 袁杰編著, “無線電高頻電路”, 全華科技圖書股份有限公司, Sep. 1992.
[10] C.Li. Liu, “Impacts of I/Q Imbalance on QPSK-OFDM-QAM Detection,” IEEE Trans. On Consumer Electronics, vol.44, no.3, pp.984-989, Aug.1998.
[11] B. Razavi, ”RF Microelectronics”, Prentice Hall, 1997.
[12] B. Razavi, “Design considerations for direct-conversion receivers” IEEE Trans. On Circuits and Systems-II: Analog and Digital Signal Processing, vol.44, no.6, June 1997.
[13] R. Hartley, ”Modulation System,” U.S. Patent 1,666.206. April 1928.
[14] D. K. Weaver, “A Third Method of Generation and Detection of Single Sideband Signal,” Proc. IRE, vol.44, pp.1703-1705, December 1956.
[15] Crols, J.; Steyaert, M.S.J.,” Low-IF topologies for high-performance analog front ends of fully integrated receivers,” Digital Object Identifier, vol.45, Issue 3, pp.269-282, March 1998
[16] B. Razavi, “A 5.2-GHz CMOS Receiver with 62-dB Image Rejection,”IEEE JSSC., vol.36, no.5, May 2001.
[17] T. H. Lee, “The Design if CMOS Radio-Frequency Integrated Circuit,” Cambridge University Press, 1998.

[18] Ryuichi Fujimoto, Kenji Kojima, and Shoji Otaka, “A 7-GHz 1.8dB NF CMOS Low Noise Amplifier,” IEEE JSSC., vol.37, pp.852-856, July 2002.
[19] David J. Allstot, Xiaoyong Li, and Sudip Shekhar, “Design Considerations for CMOS Low-Noise Amplifiers,”Radio Frequency Integrated Circuits (RFIC) Symposium, pp. 97-100, 6-8 June. 2004.
[20] Brian A. Floyd and Dicle Ozis, “Low-Noise Amplifier Comparison at 2GHz in 0.25um RF-CMOS and SiGe BiCMOS,” Radio Frequency Integrated Circuits (RFIC) Symposium, pp.185-188, IEEE 6-8, June. 2004.
[21] Devendra K. Misra “Radio-Frequency and Microwave Communication Circuits,” John Wiley & Sons, Inc., 2001.
[22] 林昂生，應用在數位音訊廣播(DAB)接收機L頻帶降頻器之CMOS單晶射頻微波積體電路，國立成功大學電機工程研究所碩士論文，民國九十年。
[23] F. Svelto, S. Deantoni, G. Montagna, and R. Castello, “Implementation of a CMOS LNA Plus Mixer for GPS Applications with No External Components,” IEEE Trans. On VLSI system, vol.9, February 2001.
[24] S. G. Lee and J. K. Choi, “Current-reuse bleeding Mixer,” Electron. Lett, vol.36, no.8, pp.696-697, April 2000.
[25] Ren-Chieh Liu; Kuo-Liang Deng; Huei Wang, “A 0.6-22-GHz broadband CMOS distributed amplifier,” Radio Frequency Integrated Circuits (RFIC) Symposium, pp.103-106, IEEE 8-10, June 2003.
[26] Chang-Wan Kim, Min-Suk Kang, Phan Tuan Anh, Hoon-Tae Kim, and Sang-Gug Lee, “An Ultra-Wideband CMOS Low Noise Amplifier for 3-5GHz UWB System,” IEEE JSSC., Feb. 2005.
[27] C.W.Kim M.s.Jung and S.G.Lee, “Ultra-wideband CMOS low noise amplifier,” IEE. electronics letters, vol.41, no.7, March 2005.
[28] B. M. Ballweber, R. Gupta, and D. J. Allstot, “A fully integrated 0.5–5.5-GHz CMOS distributed amplifier,” IEEE JSSC., vol.35, no.2, pp.231–239, Feb. 2000.
[29] F. Bruccoleri, E. A. M. Klumperink, and B. Nauta, “Noise canceling in wideband CMOS LNA’s” IEEE ISSCC Dig. Tech. Papers, vol. 1, Feb. 2002, pp. 406–407.
[30] S. Andersson, C. Svensson, and O. Drugge, “Wideband LNA for a multistandard wireless receiver in 0.18 μmCMOS,” Proc. ESSCIRC, pp. 655–658, Sep. 2003.
[31] Bendong Sun, Fei Yuan and Ajoy Opal, “Inductive peaking in wideband CMOS current amplifiers,” IEEE ISCAS, 2004.
[32] Ismail, A.; Abidi, A.A., “A 3-10-GHz low-noise amplifier with wideband LC-ladder matching network,” IEEE JSSC., vol.39, Issue 12, pp.2269-2277, Dec. 2004.
[33] Trung-Kien Nguyen; Chung-Hwan Kim; Gook-Ju Ihm; Moon-Su Yang; Sang-Gug Lee, “CMOS low-noise amplifier design optimization techniques,”, IEEE Trans. On Microwave Theory and Techniques, vol.52, Issue 5, pp.1433-1442, May 2004.