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研究生:林晉禾
研究生(外文):Lin, Jin-Ho
論文名稱:ARMv4指令集架構相容之微處理器智財設計與驗證
論文名稱(外文):The Design and Verification of an ARM v4 Instruction Set Architecture Compatible Microprocessor IP
指導教授:林銘波林銘波引用關係
指導教授(外文):Lin, Ming-Bo
學位類別:碩士
校院名稱:國立臺灣科技大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2005
畢業學年度:93
語文別:中文
論文頁數:76
中文關鍵詞:微處理器智財
外文關鍵詞:ARMMicroprocessorIP
相關次數:
  • 被引用被引用:7
  • 點閱點閱:244
  • 評分評分:
  • 下載下載:44
  • 收藏至我的研究室書目清單書目收藏:1
  在本論文中,我們設計與實現了一個與ARM v4指令集架構相容的微處理機智財(Intellectual Property, IP)─Proto-ARM9M。由於智財的可重複利用性是建立在智財驗證的完整度上,因此本論文也建立一套完整的測試環境,可用來驗證智財的行為層(behavioral level)、暫存器轉移層(regisiter transfer level)、合成後閘級層(post-synthesized gate level)與佈局後閘級層(post-layout gate level)之設計。
  我們根據ARM v4指令集架構的行為描述來設計Proto-ARM9M的行為層模型,並同時設計整個測試環境的架構。在行為層模型驗證成功之後,我們著手暫存器轉移層模型的設計,將5級管線架構的概念導入Proto-ARM9M的資料路徑(data path)中,並針對資料路徑中的指令解碼器(instruction decoder)、暫存器陣列(register file)、移位器(shifter)、算術邏輯單元(arithmetic and logic unit)、乘加器(multiply-accumulator)與程式狀態暫存器(program status register)做特別的設計,以加增加整體效能並減少面積的消耗。暫存器轉移層模型在測試平台的模擬結果與ARM指令集模擬器ADS(ARM Developer Suite)相同,模擬的平均程式涵蓋率(code coverage)可達96.58%。
  Proto-ARM9M微處理器智財已分別在Xilinx的Spartan-3 XC3S1500-4FG676 FPGA以及TSMC 0.35 μm元件庫上實現。在FPGA設計部分,消耗了9304個LUT,最高操作頻率為21 MHz,並在實驗板上成功的驗證所有個測試程式。在元件庫方面,核心面積為3420.8 μm × 3212.5 μm,等效閘數(gate count)為55450閘,整體晶片面積則為5251.8 μm × 5087.4 μm,在SS(Slow NMOS Slow PMOS model)模式下操作頻率為33.33 MHz,平均消耗功率為151.2 mW ~ 192.8 mW。
In this thesis, an ARM v4 instruction set architecture compatible microprocessor IP (Intellectual Property), Proto-ARM9M, is proposed. Since the reusability of IP depends on the completeness of its verification, we also develop a test environment to demonstrate IP accuracy on each steps of ASIC design flow, such as behavioral level, register transfer level, post-synthesized gate level, and post-layout gate level model.
Based on the behavior of ARM v4 instruction set architecture, we design the behavioral-level model of Proto-ARM9M, and establish a test environment to verify it. After the behavioral-level model verification is done, we start to design register-transfer-level model of Proto-ARM9M. A typical five-stage pipeline is used in the Proto-ARM9M datapath. The individual module of datapath, such as instruction decoder, register file, shifter, arithmetic and logic unit, multiply-accumulator, and program status register are designed carefully to improve performance and decrease area. The register-transfer-level simulation results in the testbech are the same as ARM instruction simulator, ADS (ARM Developer Suite), and the average code coverage of every module in Proto-ARM9M is 96.58%.
Proto-ARM9M has been implemented and verified with Xilinx Spartan-3 XC3S1500-4FG676 FPGA and TSMC 0.35 μm cell library. In the FPGA part, it takes 9304 LUTs and operates at the maximum working frequency of 21 MHz. Furthermore, all of the testing programs are run successfully in FPGA development board. In the cell-based part, the core occupies 3420.8 μm 3212.5 μm, which is approximately equivalent to 55450 gates, and the whole chip occupies 5251.8 μm 5087.4 μm. Proto-ARM9M consumes about 151.2 mW to 192.8 mW in the SS(Slow NMOS Slow PMOS model)simulation condition at the maximum working frequency of 33 MHz.
第1章 緒論 1
1.1 研究動機 1
1.2 章節編排 1
第2章 ARM微處理器簡介 3
2.1 ARM的發展現況 3
2.2 程式模型(PROGRAM MODEL) 3
2.3 指令集架構(INSTRUCTION SET ARCHITECTURE) 7
第3章 PROTO-ARM9M的系統架構 11
3.1 ARM9TDMI的簡介 11
3.2 PROTO-ARM9M的特性 12
3.3 系統架構簡介 13
3.4 資料路徑 15
3.5 時序說明 17
3.6 控制方法 18
3.7 危障處理 19
3.8 例外處理 22
第4章 PROTO-ARM9M資料路徑的設計 25
4.1 指令解碼器(INSTRUCTION DECODER, ID) 25
4.2 暫存器陣列(REGISTER FILE) 28
4.3 移位器(SHIFTER) 32
4.4 算術邏輯單元(ARITHMETIC AND LOGIC UNIT, ALU) 35
4.5 乘加器(MULTIPLY-ACCUMULATOR, MAC) 37
4.6 程式狀態暫存器(PROGRAM STATUS REGISTER, PSR) 42
第5章 PROTO-ARM9M的控制單元 45
5.1 資料路徑的控制 45
5.2 LDM / STM指令的控制 49
5.3 SWP 指令的控制 51
第6章 PROTO-ARM9M矽智財的實現和驗證 53
6.1 行為層和暫存器轉移層的設計流程 53
6.2 PROTO-ARM9M矽智財的驗證流程 54
6.3 測試程式與程式涵蓋率(CODE COVERAGE) 57
第7章 FPGA的驗證與結果分析 61
7.1 FPGA的驗證流程 61
7.2 FPGA合成與自動繞線的結果分析 62
7.3 FPGA驗證系統之設計 63
第8章 元件庫的實現與效能評估 66
8.1 元件庫設計的實現與驗證流程 66
8.2 合成 66
8.3 DFT與ATPG 67
8.4 自動化佈局 70
第9章 結論 75
參考文獻 76
[1]Steve Furber, ARM System-on-Chip Architecture, Addison-Wesley, 2000.
[2]http://www.arm.com
[3]ARM Architecture Reference Manual, ARM Ltd, 2000
[4]ARM Instruction Set Quick Reference Card, ARM Ltd, 1999.
[5]Simon Segars, The ARM9 Family – High Performance Microprocessors for Embedded Applications, IEEE International Conference on Computer Design 1999 (ICCD’99).
[6]ARM9TDMI Technical Reference Manual, ARM Ltd, 2000
[7]J. L. Hennessy and D. A. Patterson, Computer Organization and Design: The Hardware / Software interface, 3rd ed., Morgan Kaufmann, 2003.
[8]J. L. Hennessy and D. A. Patterson, Computer Architecture: A Quantitative Approach, 3rd ed., Morgan Kaufmann, 2003.
[9]林銘波,數位系統設計 – 原理、實務與 ASIC 實現,第三版,全華科技圖書股份有限公司,2002。
[10]Behrooz Parhami, Computer Arithmetic: Algorithms and Hardware Designs, Oxford University Press, New York, 2000.
[11]Janick Bergeron, Writing Testbenches Functional Verification of HDL Models, MA: Kluwer Academic Publishers, 2000.
[12]Andrew N. Sloss, Dominic Symes and Chris Wright, ARM System Developer’s Guide, Morgan Kaufmann, 2004.
[13]Michael Keating and Pierre Bricaud, Reuse Methodology Manaul: For System – On – a – Chip Design, 3rd ed., MA: Kluwer Academic Publishers, 2002.
[14]PrimeTime User Guide: Advanced Timing Analysis, Synopys Ltd, 2003.
[15]PrimePower Maunual, Synopys Ltd, 2003.
[16]3.3 V 64 K × 32/36 Flow Through Synchronous SRAM Data Sheet, Alliance Semiconductor Ltd, 2005.
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