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研究生:丘仲翔
研究生(外文):Chiu Chung-Hsiang
論文名稱:雙斜率高解析度之時間至數位轉換器
論文名稱(外文):A Dual-Slope, High-Accuracy Time-to-Digital Converter
指導教授:陳伯奇陳政寰陳政寰引用關係
學位類別:碩士
校院名稱:國立臺灣科技大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2005
畢業學年度:93
語文別:中文
論文頁數:99
中文關鍵詞:時間至數位轉換器
外文關鍵詞:Time-to-Digital ConverterTDC
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在本論文中提出一高解析度之時間至數位轉換器,基於改善溫度、製程等外在環境因素對電路特性的影響,使用鎖相迴路(Phase Lock Loop, PLL)來產生穩定的週期訊號,此外利用雙斜率內插器(Dual-Slope Interpolator)將時間等效放大的原理來提高本電路之解析度,另外透過可觸發振盪器之設計使得起始訊號與振盪週期上升邊產生同步,藉由此機制可減少一組內插器之使用,對於成本有一定之改善。
本論文的電路製作是以TSMC 0.35 2P4M的製程來實現,TDC的解析度高達25ps,晶片面積含接墊(I/O PAD)為875 um * 420 um,經模擬可得整體非線性誤差落在-0.8LSB~0.8LSB以內,量測的轉換時間小於等於204.8ns。
This research presents a high resolution Time-to-Digital Converter. In order to eliminate the influence of the element mismatch and the temperature variation, the phase-locked loops circuit is used to produce stable system clock. The separate time digitizer improves the time resolution by interpolating within the clock period. The interpolator is based on analog dual-slope conversion. Furthermore, the trigger voltage controlled oscillator is utilized to make start pulse synchronous with system clock. It could reduce one interpolator and has the improvement in cost.
The Time-to-Digital Converter with 25-ps resolution and had been integrated in 0.35-μm standard 2P4M CMOS technology. The size of this chip, not including pads, is 875-μm * 420-μm. According to simulation results, the integral nonlinearity is 0.8LSB and the conversion time is within 204.8-ns.
中文摘要-------------------------------------------------------------I
英文摘要------------------------------------------------------------II
誌謝---------------------------------------------------------------III
目錄----------------------------------------------------------------IV
圖目錄-------------------------------------------------------------VII
表目錄---------------------------------------------------------------X


第一章 緒論
1-1 研究動機------------------------------------------------------1
1-2 內容編排方式--------------------------------------------------3

第二章 時間至數位轉換器
2-1 時間至數位轉換器簡介-------------------------------------------4
2-2 計數器方法之時間至數位轉換器------------------------------------5
2-3 起始–停止原理之時間至數位轉換器--------------------------------8
2-3.1 雙斜率法(Dual Slope)-----------------------------------8
2-3.2 時間至振幅轉換法----------------------------------------9
2-4 游標尺延遲線之時間至數位轉換器---------------------------------10
2-5 線性互補金氧半時間至數位轉換器---------------------------------14
2-6 循環式時間至數位轉換器----------------------------------------17
2-6.1 脈衝縮減原理-------------------------------------------19
2-6.2 循環式時間至數位轉換器----------------------------------22
2-7 各種方法的比較-----------------------------------------------24

第三章 雙斜率高解析度之時間至數位轉換器
3-1 文獻回顧----------------------------------------------------26
3-1.1 介穩態的說明-------------------------------------------32
3-2 雙斜率高解析度之時間至數位轉換器-------------------------------35
3-3 鎖相迴路的設計與製作------------------------------------------37
3-3.1 相位頻率偵測器-----------------------------------------39
3-2.2 充電幫浦----------------------------------------------47
3-2.3 迴路濾波器---------------------------------------------51
3-2.4 電壓控制震盪器-----------------------------------------52
3-2.5 除頻器------------------------------------------------60
3-4 時間至脈衝控制電路--------------------------------------------61
3-5 內插器電路---------------------------------------------------63
3-5.1 比較器------------------------------------------------65
3-6 輸出計數器---------------------------------------------------70

第四章 電路模擬與晶片佈局
4-1 設計流程與規格需求-------------------------------------------71
4-2 本論文所提出之TDC的模擬---------------------------------------74
4-2.1 相位鎖定迴路的模擬--------------------------------------74
4-2.2 時間至脈衝控制區塊的模擬--------------------------------81
4-2.3 雙斜率內插器的模擬--------------------------------------82
4-2.4 時間至數位轉換器的模擬----------------------------------84
4-3 晶片佈局----------------------------------------------------91

第五章 結論
5-1 結論--------------------------------------------------------93

參考文獻------------------------------------------------------------94
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