臺灣博碩士論文加值系統

本論文設計一高解析度四階前饋式和差類比數位轉換器。由於在高階電路且具有回授電路的架構中，由係數決定穩定性的問題是非常難推導的，且在HSPICE中的模擬是非常耗時的。因此在此論文中我們提供了一個決定係數的完整流程，也可以減少在模擬時所需要的時間。並且在電路設計上提供了一個二階對稱性疊接運算放大器、交換式電容電路及一個低功率消耗的比較器。採用TSMC 3.3V 0.35μm 2P4M製程，在超取樣率為256，輸入訊號是20k Hz時，可以得到75.1dB的最大訊號雜訊比(相當於12.5位元的解析度)，而功率消耗為30.9mW。

A fourth-order cascade-of-integrator feedforward sigma-delta A/D converter is presented in this paper. The stability that is decided by the coefficient we choose is a problem for the architecture of high order with a feedback path that would waste much time to be simulated by HSPICE. Hence, we provide a complete design to choose the coefficient so that we can save time in simulation. We design a two-stage differential folded-cascode operational amplifier, switched-capacitor circuits, and a low power comparator. This modulator is implemented by TSMC 3.3V 0.35μm 2P4M mixed signal process, with the oversampling rate of 256 and signal bandwidth of 20k Hz. We can have the biggest signal-to-noise ratio as 75.1dB, and the power consumption is 30.9mW.

Abstract (in Chinese)......................................................I
Abstract (in English) ....................................................II
Acknowledgement (in Chinese).............................................III
Contents..................................................................IV
List of Figures..........................................................VII
List of Tables.............................................................X


Chapter 1 Introduction
1.1 Motivation.......................................................1
1.2 Organization.....................................................3
Chapter 2 Sigma-Delta Modulator Fudamentals
2.1 Nyquist Rate Converters...........................................................4
2.1.1 Nyquist Rate.................................................................5
2.1.2 Quantization Error................................................................6
2.1.3 Kinds of Nyquist Rate Converter............................................................8
2.2 Oversampling Converters...........................................................9
2.2.1 Oversampling..................................................10
2.2.2 Noise Shaping.............................................................12
2.2.2.1 First-Order Sigma-Delta with Noise Shaping.............13
2.2.2.2 Second-Order Sigma-Delta with Noise Shaping............17
2.3 Sigma-Delta A/D Converter Architecture..........................21
2.3.1 Single-Loop Architecture........................................................21
2.3.1.1 Cascade-of-Inegrators FeedBack Form (CIFB) ..........................22
2.3.1.2 Cascade-of-Inegrators FeedForward Form (CIFF) .....................23
2.3.2 Multi-Loop Architecture...........................................................................25
2.3.3 Single-Bit Architecture.............................................................................26
2.3.4 Multi-Bit Architecture...............................................................................26
2.4 Summary..............................................................................................................27
Chapter 3 System Design
3.1 Switched-Capacitor Circuit..................................................................................29
3.1.1 Switched-Capacitor Theorem...................................................................30
3.1.2 Switched-Capacitor Integrator..................................................................31
3.2 Non-Ideal Consideration......................................................................................33
3.2.1 Thermal Noise...........................................................................................33
3.2.2 Finite Gain of the Operational Amplifier..................................................36
3.2.3 Clock Jitter................................................................................................38
3.3 Modeling CIFF Sigma-Delta Modulator.............................................................40
3.3.1 Decide the Coefficient of Each Stage.......................................................40
3.3.2 Simulate by Matlab Simulink...................................................................44
3.4 Summary..............................................................................................................46
Chapter 4 Circuit Implementation
4.1 The Design of Operational Amplifier..................................................................47
4.2 The Design of Integrator......................................................................................54
4.2.1 The Design of The First Stage..................................................................55
4.2.2 The Design of The Second to Fourth Stage..............................................56
4.2.3 The Design of The Analog Adder.............................................................57
4.3 The Design of The Quantizer Design..................................................................59
4.3.1 The Design of The Comparator................................................................59
4.3.2 SR_Latch..................................................................................................62
4.4 The Design of 1-Bit Digital-to-Analog Circuit....................................................64
4.5 The Design of Non-Overlap Two-Phase Clock Generator..................................66
4.6 Layout..................................................................................................................68
4.7 Simulation Results...............................................................................................70
4.8 The Result of Measurement....................................................................................72
4.9 Summary.................................................................................................................74
Chapter 5 Conclusion
5.1 Conclusion...........................................................................................................74
5.2 Future Work.........................................................................................................75
Reference...................................................................................................................76

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