臺灣博碩士論文加值系統

離散小波轉換（Discrete Wavelet Transform, DWT）是一種訊號轉換的演算法，其具有將訊號分解成不同頻帶的特性，因而被應用在多重解析度的訊號分析上，在影像壓縮技術中（如：JPEG2000與MPEG4），離散小波轉換也因為高壓縮比、低失真的特性，相當適合應用在低位元率的影像壓縮。
傳統離散小波轉換是以濾波器為主，由於所需的計算量相當龐大，因此，新一代的小波--上提式離散小波轉換(Lifting-based DWT)在1996年被提出。其低運算複雜度的特性，也使得上提式離散小波較傳統小波轉換更適合以硬體的方式實現，而影像標準JPEG 2000也以上提式離散小波為其主要的壓縮標準之一。
本篇論文中，我們分成兩部分，首先我們設計了一個二維的上提式離散小波轉換，利用線緩衝器來儲存行處理所需的中間值，使的行與列能同時處理，完成一張 的影像只需要 個時脈，此外針對小波轉換其二分之一取樣而造成的硬體使用率低的缺點，我們使用管線化與乘法器共用的特性來提高硬體使用率。第二個部分則是透過外部記憶體的使用與部分控制線路，使得我們的設計能處理的階數與影像的大小，均能參數化的調整。
最後以Verilog HDL 實現所提出的電路架構，再使用Synopsys的Design Compiler 進行邏輯合成，經過Apollo Layout Tools配合TSMC的0.35μm 1P4M CMOS製程技述自動合成出的佈局圖，其模擬出來的Gate count 為31093，工作時脈則為83MHZ，其Core Area為1740*1670 。

Discrete wavelet transform (DWT) is an algorithm with multi-resolution that can decompose data or signal into several components in different octave bands. In the image compression (eg. JPEG-2000 or MPEG-4), DWT can be apply on the low bit-rate compression because of its low distortion.
Traditionally, DWT has been implemented by filters which require a large size of storage and complex computations. In 1996, the lifting scheme [2], a new method for constructing biorthogonal wavelet was proposed for DWT. Since the lifting scheme has several advantages, such as less hardware resource and faster computation speed. The lifting-based DWT is also used in the newest image standard - JPEG-2000.
In this paper, we propose two parts of 2-D DWT architectures. In the first part, we present an non-separable architecture for 2-dimensional lifting-based DWT. Because of downsampling of the DWT, the hardware utilization is very low. In order to solve the problem, we propose a merged and line buffer architecture, which combines the horizontal and vertical DWT together. In the second part, we add external memory and some control circuits to make the architecture suitable for different decomposition levels. Parametric design makes our circuit that can process different size of image and decomposition levels.
The proposed VLSI architectures are described in Verilog HDL, and synthesized by the Synopsys’ Design Compiler. Finally, the layout of the design is generated automatically by the Avant! Apollo Layout Tools in a 0.35 1P4M CMOS technology. The Gate count number is 31093, and the clock frequency is 83MHZ.

摘 要 IV
ABSTRACT V
致 謝 VI
目 次 VII
圖 目 錄 IX
表 目 錄 XI
第一章 緒論 1
1.1 研究背景與動機 1
1.2 相關研究 2
1.3 章節概要 3
第二章 離散小波轉換 5
2.1 前言 5
2.2 傳統離散小波轉換 6
2.3 上提式離散小波轉換 8
2.3.1 上提式離散小波正轉換 9
2.3.2上提式離散小波反轉換 10
2.3.3 與傳統離散小波之比較 12
2.4 一維多階離散小波轉換 13
2.5 二維離散小波轉換 14
2.5.1 二維一階離散小波轉換 14
2.5.2 二維多階離散小波轉換 16
2.5.3 應用於影像處理 17
第三章 5/3濾波器之二維上提式離散小波轉換架構 19
3.1 前言 19
3.2上提式5/3濾波器DWT之VLSI實現 20
3.3 直接實現 22
3.4 設計概念 23
3.4.1 二維影像之設計概念 23
3.4.2 列轉換 25
3.4.3 行轉換 26
3.5 二維小波轉換硬體架構 29
3.6 多階的設計 35
第四章 模擬與結果 38
4.1設計流程 38
4.2 效能與結果 38
4.3 模擬結果 40
第五章 結論 43
參考文獻 44

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