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研究生:李明璋
研究生(外文):Ming-Chang Lee
論文名稱:可參數化之高速維特比解碼IP產生器
論文名稱(外文):Parameterized IP Generator for High-Speed Viterbi Decoding
指導教授:張郁斌
指導教授(外文):Yu-Pin Chang
學位類別:碩士
校院名稱:南台科技大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2006
畢業學年度:94
語文別:中文
論文頁數:48
中文關鍵詞:迴旋碼維特比高速
外文關鍵詞:convolution codeViterbihigh-speed
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在數位通訊系統領域中,維特比演算法(Viterbi Algorithm)為一公認的有效的近似解碼演算法,並已廣泛地應用在迴旋碼之解碼。迴旋碼因為具有良好的錯誤控制能力﹙Error- Control Performance﹚而廣泛地被應用在各通訊系統,例如行動電話、無線通訊、數位電視、數位廣播等等。
本論文使用MSB-first ACSU架構以加速Viterbi解碼器的整體處理速度。在實現高速Viterbi解碼器時,其內部的ACS單元為主要瓶頸,但是藉著在ACS單元內的各Critical Path之間取得平衡,且縮短各Critical Path之間的差距,以縮短Viterbi整體的Critical Path,提升速度。同時,使用者可自行調整碼率及記憶級數等設計參數,提供了有效且具彈性的通道解碼功能的實現,經由IP 模組化設計,使用者可有效加速晶片設計與實現之時程、降低開發的成本、提升性能及效率。
The Viterbi algorithm, widely used in digital communication systems, is known to be an efficient method for the realization of maximum likelihood decoding of convolution codes. Convolution codes are widely used in many communication systems due to their excellent error control performance.
In this thesis, a most-significant-bit (MSB)-first ACS unit is used to implement a high speed Viterbi decoder. The ACS unit is the main bottleneck on the decoding speed of a Viterbi decoder. By balancing the settling time of different paths in the ACS unit, the length of the critical path is reduced as close as possible to the iteration bound in the ACS unit. We supply a flexible IP implementation of channel decoding to easily adjust code rate and memory progression variable. With the help of our IP modules, the chip design time can be reduced efficiency.
摘 要 IV
ABSTRACT V
誌謝 VI
第一章 簡介 1
1.1 前言 1
1.2矽智產簡介 2
1.3研究動機與目的 3
1.4 章節概論 4
第二章 迴旋碼與維特比演算法 5
2.1 迴旋碼(Convolutional code) 5
2.2 維特比演算法(Viterbi Algorithm) 9
第三章 高速維特比解碼器之架構 16
3.1 維特比解碼器之主要單元 16
3.1.1 蝴蝶模組(Butterfly Module) 17
3.1.2 分支計量運算單元(BMU) 19
3.1.3 加-比較-選擇運算單元(ACSU) 20
3.1.4 存活記憶體單元(SMU) 22
3.2 硬體架構分類 22
3.3 Bit-Level Parallelization 23
3.4 Look-Ahead Technique 27
3.5 Retiming Cut-Set 29
第四章 高速維特比IP產生器之實現 36
4.1 可參數化通道編解碼IP模組產生器 36
4.2 規格與應用 37
4.3 IP產生器之驗證 39
4.4 數據比較 43
第五章 結論 44
附錄A 適用於腓特比解碼器之迴旋碼碼率 45
參考文獻 46
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[16] Gerhard Fettweis, and Heinrich Meyr, “A 100MBIT/S VITERBI DECODER CHIP : NOVEL ARCHITECTURE AND ITS REALIZATION,” 1990, IEEE.
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[21] R.Burger, G Cesana, M. Paolini, M. Turolla, S. Vercelli, “A Fully Synthesizable Parameterized Viterbi Decoder,” IEEE Custom Integrated Circuits Conference,1999.
[22] 葉丞淵,具多目標式腓特比解碼器之矽智財產生器,國立台北科技大學,電腦通訊與控制研究所,碩士論文,民91年。
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